• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.87-97
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• 2013

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM $V_{MIN}$, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM $V_{MIN}$. Two different types of SRAM $V_{MIN}$ (SNM-limited $V_{MIN}$ and time-limited $V_{MIN}$) are explained. Simulation results show that SNM-limited $V_{MIN}$ is more sensitive to NBTI while time-limited $V_{MIN}$ is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the $V_{MIN}$ degradation induced by NBTI/PBTI.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.151-157
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• 2013

In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

• Proceedings of the Korean Society of Computer Information Conference
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• 2023.01a
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• pp.213-215
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• 2023

본 논문은 "PBTI"라 명명한 웹사이트를 설계하고 구현한다. 요즘 유행하는 성격 유형 설문조사인 MBTI에서 영감을 받아 피부타입과 퍼스널 컬러를 검사할 수 있는 온라인 쇼핑몰 웹사이트를 제작하게 되었다. 체계적이고 다양한 질문을 통해 사용자들의 피부타입을 검사하고 해당 피부타입 결과에 따른 상품을 추천해주는 알고리즘이 탑재되어 사용자에 맞는 상품을 추천해준다. PBTI의 이러한 기능들은 다른 온라인 뷰티쇼핑몰과 극명한 차별점을 만들고, 쇼핑몰 매출을 크게 증대시킬 것으로 기대한다. 데이터베이스를 구축하기 위해 오라클을 이용하였고, 웹페이지를 구현하기 위해 스프링을 이용하였으며 팀원들과의 협업을 위해 깃허브를 사용하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.180-186
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• 2023

Positive bias temperature instability (PBTI) degradation of n⁺ and p⁺ poly-Si gate high-voltage(HV) SiO2 dielectric nMOSFETs was investigated. Unlike the expectation that degradation of n⁺/nMOSFET will be greater than p⁺/nMOSFET owing to the oxide electric field caused by the gate material difference, the magnitude of the PBTI degradation was greater for the p⁺/nMOSFET than for the n⁺/nMOSFET. To analyze the cause, the interface state and oxide charge were extracted for each case, respectively. Also, the carrier injection and trapping mechanism were analyzed using the carrier separation method. As a result, it has been verified that hole injection and trapping by the p⁺ poly-Si gate accelerates the degradation of p⁺/nMOSFET. The carrier injection and trapping processes of the n⁺ and p⁺ poly-Si gate high-voltage nMOSFETs in PBTI are detailed in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.8-14
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• 2012

The device performances of n-channel MuGFET with different fin numbers and fin widths but the total effective channel width is constant have been characterized. Two kinds of Pi-gate devices with fin number=16, fin width=55nm, and fin number=14, fin width=80nm have been used in characterization. The threshold voltage, effective electron mobility, threshold voltage roll-off, inverse subthreshold slope, PBTI, hot carrier degradation, and drain breakdown voltage have been characterized. From the measured results, the short channel effects have been reduced for narrow fin width and large fin numbers. PBTI degradation was more significant in devices with large fin number and narrow fin width but hot carrier degradation was similar for both devices. The drain breakdown voltage was higher for devices with narrow fin width and large fin numbers. With considering the short channel effects and device degradation, the devices with narrow fin width and large fin numbers are desirable in the device layout of MuGFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.166-173
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• 2009

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.

• Proceedings of the Korean Society of Computer Information Conference
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• 2023.07a
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• pp.705-708
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• 2023

본 논문은 사용자의 피부 상태에 따라 사용자에게 적합한 화장품을 소개해주는 화장품 추천 웹 쇼핑몰, "PBTI"를 개발한다. 요즘 유행하는 성격 유형 설문조사인 MBTI에서 영감을 받아 피부 유형과 퍼스널 컬러를 검사하고 이를 기반으로 화장품을 추천하는 온라인 쇼핑몰 웹사이트를 제작하게 되었다. 바우만 교수의 피부 유형 지표를 바탕으로 제작된 질문을 통해 사용자들의 피부 유형을 검사하고 해당 피부 유형 결과에 따른 상품을 추천해주는 알고리즘이 탑재되어 사용자에게 맞는 상품을 추천해준다. 텐서플로우 기반의 인공지능을 탑재하여 퍼스널컬러 테스트를 제작하였다. PBTI의 이러한 무료 테스트 서비스 제공은 다른 온라인 뷰티 쇼핑몰과 극명한 차별점을 만들고, 쇼핑몰 매출을 크게 증대시킬 것으로 기대한다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.3
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• pp.182-187
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• 2011

In this paper, PBTI characteristics of NMOSFETs with La incorporated HfSiON and HfON are compared in detail. The charge trapping model shows that threshold voltage shift (${\Delta}V_{\mathrm{T}}$) of NMOSFETs with HfLaON is greater than that of HfLaSiON. PBTI lifetime of HfLaSiON is also greater than that of HfLaON by about 2~3 orders of magnitude. Therefore, high charge trapping rate of HfLaON can be explained by higher trap density than HfLaSiON. The different de-trapping behavior under recovery stress can be explained by the stable energy for U-trap model, which is related to trap energy level at zero electric field in high-k dielectric. The trap energy level of two devices at zero electric field, which is extracted using Frenkel-poole emission model, is 1,658 eV for HfLaSiON and 1,730 eV for HfLaON, respectively. Moreover, the optical phonon energy of HfLaON extracted from the thermally activated gate current is greater than that of HfLaSiON.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.147-147
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• 2009