• 한국재료학회지
• /
• 제24권9호
• /
• pp.443-450
• /
• 2014

Amorphous (a-Si) films were epitaxially crystallized on a very thin large-grained poly-Si seed layer by a silicide-enhanced rapid thermal annealing (SERTA) process. The poly-Si seed layer contained a small amount of nickel silicide which can enhance crystallization of the upper layer of the a-Si film at lower temperature. A 5-nm thick poly-Si seed layer was then prepared by the crystallization of an a-Si film using the vapor-induced crystallization process in a $NiCl_2$ environment. After removing surface oxide on the seed layer, a 45-nm thick a-Si film was deposited on the poly-Si seed layer by hot-wire chemical vapor deposition at $200^{\circ}C$. The epitaxial crystallization of the top a-Si layer was performed by the rapid thermal annealing (RTA) process at $730^{\circ}C$ for 5 min in Ar as an ambient atmosphere. Considering the needle-like grains as well as the crystallization temperature of the top layer as produced by the SERTA process, it was thought that the top a-Si layer was epitaxially crystallized with the help of $NiSi_2$ precipitates that originated from the poly-Si seed layer. The crystallinity of the SERTA processed poly-Si thin films was better than the other crystallization process, due to the high-temperature RTA process. The Ni concentration in the poly-Si film fabricated by the SERTA process was reduced to $1{\times}10^{18}cm^{-3}$. The maximum field-effect mobility and substrate swing of the p-channel poly-Si thin-film transistors (TFTs) using the poly-Si film prepared by the SERTA process were $85cm^2/V{\cdot}s$ and 1.23 V/decade at $V_{ds}=-3V$, respectively. The off current was little increased under reverse bias from $1.0{\times}10^{-11}$ A. Our results showed that the SERTA process is a promising technology for high quality poly-Si film, which enables the fabrication of high mobility TFTs. In addition, it is expected that poly-Si TFTs with low leakage current can be fabricated with more precise experiments.

• Journal of Information Display
• /
• 제13권2호
• /
• pp.61-66
• /
• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
• /
• pp.1101-1104
• /
• 2008

We have fabricated the transparent TFTs using new oxide material (AZTO: Al-doped zinc tin oxide) as an active layer. The AZTO TFT showed good performance without post-annealing. The electrical characteristics were improved by the post-annealing up to $300^{\circ}C$. The AZTO TFTs exhibited a mobility of $8{\sim}12\;cm^2/Vs$, a sub-threshold swing of 0.2~0.6 V/dec, and an on/off ratio of more than $10^9$.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.12-12
• /
• 2010

Time dependence of the shift of the threshold voltage of amorphous hafnium-indium-zinc oxide (a-HIZO) has been reported under on-current stress condition. a-HIZO thin films were deposited on $SiO_2$/Si (100) by rf magnetron sputtering. XPS measurement indicates that the Hf metal cations in a-HIZO system after annealing process reduce oxygen vacancies by binding oxygen. It was found that the Hf metal cation can be effectively incorporated in the IZO thin films as a suppressor against both the oxygen deficiencies and the carrier generation in the ZnO-based system.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
• /
• pp.165-165
• /
• 2014

In this study, we demonstrated that the soft lithographic patterning processing of chemical vapor deposition (CVD) graphene and rGO sheets as large scale, low cost, high quality and simplicity for future industrial applications. Recently, a previous study has reported that single layer graphene grown via CVD was patterned and transferred to a target surface by controlling the surface energy of the polydimethylsiloxane (PDMS) stamp [1]. Using this approach, the surface of a relief-patterned elastomeric stamp was functionalized with hydrophilic dimethylsulfoxide (DMSO) molecules to enhance the surface energy of the stamp and to remove the graphene-based layer from the initial substrate and transfer it to a target surface [2]. Further, we developed a soft lithographic patterning process via surface energy modification for advanced graphene-based flexible devices such as transistors or simple and efficient chemical sensor consisting of reduced graphene oxide (rGO) and a metallic nanoparticle composite. A flexible graphene-based device on a biocompatible silk fibroin substrate, which is attachable to an arbitrary target surface, was also successfully fabricated.

• 한국진공학회지
• /
• 제16권5호
• /
• pp.359-365
• /
• 2007

본 논문에서는 zinc oxide (ZnO)와 gallium이 도핑 된 zinc oxide (GZO)를 이용하여 radio frequency (RF) magnetron sputtering 방법에 의해 상온에서 제작된 bottom-gate 박막 트랜지스터의 특성을 평가하고 분석하였다. 게이트 절연층 물질로서 새로운 물질을 사용하지 않고 열적 성장된 $SiO_2$를 사용하여 게이트 누설 전류를 수 pA 수준까지 줄일 수 있었다. ZnO와 GZO 박막의 표면 제곱평균제곱근은 각각 1.07 nm, 1.65 nm로 측정되었다. 그리고 ZnO 박막은 80% 이상, GZO 박막은 75% 이상의 투과도를 가지고 있었고, 박막의 두께에 따라 투과도가 달라졌다. 또한 두 시료 모두 (002) 방위로 잘 정렬된 wurtzite 구조를 가지고 있었다. 제작된 ZnO 박막 트랜지스터는 2.5 V의 문턱 전압, $0.027\;cm^2/(V{\cdot}s)$의 전계효과 이동도, 104의 on/off ratio, 1.7 V/decade의 gate voltage swing 값들을 가지고 있었고, enhancement 모드 특성을 가지고 있었다. 반면에 GZO 박막 트랜지스터의 경우에는 -3.4 V의 문턱 전압, $0.023\;cm^2/(V{\cdot}s)$의 전계효과 이동도, $2{\times}10^4$의 on/off ratio, 3.3 V/decade의 gate voltage swing 값들을 가지고 있었고, depletion 모드 특성을 가지고 있었다. 우리는 기존의 ZnO와 1wt%의 Ga이 도핑된 ZnO를 이용하여 두 가지 모드의 트랜지스터 특성을 보이는 박막 트랜지스터를 성공적으로 제작하고 분석하였다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.154-154
• /
• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• ETRI Journal
• /
• 제37권6호
• /
• pp.1135-1142
• /
• 2015

Multilayered ZnO-$SnO_2$ heterostructure thin films consisting of ZnO and $SnO_2$ layers are produced by alternating the pulsed laser ablation of ZnO and $SnO_2$ targets, and their structural and field-effect electronic transport properties are investigated as a function of the thickness of the ZnO and $SnO_2$ layers. The performance parameters of amorphous multilayered ZnO-$SnO_2$ heterostructure thin-film transistors (TFTs) are highly dependent on the thickness of the ZnO and $SnO_2$ layers. A highest electron mobility of $43cm^2/V{\cdot}s$, a low subthreshold swing of a 0.22 V/dec, a threshold voltage of 1 V, and a high drain current on-to-off ratio of $10^{10}$ are obtained for the amorphous multilayered ZnO(1.5nm)-$SnO_2$(1.5 nm) heterostructure TFTs, which is adequate for the operation of next-generation microelectronic devices. These results are presumed to be due to the unique electronic structure of amorphous multilayered ZnO-$SnO_2$ heterostructure film consisting of ZnO, $SnO_2$, and ZnO-$SnO_2$ interface layers.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2009년도 제40회 하계학술대회
• /
• pp.1268_1269
• /
• 2009

This work shows the effect of rapid thermal annealing (RTA) on properties of indium-zinc oxide (IZO) thin films. The RTA temperatue was controlled between 300 and $500^{\circ}C$ under the two different ambient conditions such as vacuum and oxygen. Structural, optical, and electrical properties of IZO films were characterized in terms of RTA conditions. XRD and resistivity measurements showed that crystallization for IZO films occurred at an RTA temperature of about $400^{\circ}C$. For the IZO film treated at $500^{\circ}C$ of RTA, the resistivity, carrier concentration, hall mobility, and transmittance were approximately $10^2{\Omega}cm$, $10^{15}cm^{-3}$, $10cm^2/V{\cdot}s$, and 85%, respectively, which would be suitable for its application to the channel layer in transparent thin film transistors.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2012년도 춘계학술발표대회
• /
• pp.77.1-77.1
• /
• 2012

Zn 기반 산화물 반도체는 기존의 비정질 Si에 비해 저온공정에도 불구하고 높은 이동도, 투명하다는 장점으로 인해 차세대 디스플레이용 백플레인 소자로 주목받고 있다. 산화물 트랜지스터는 우수한 소자특성을 보여주고 있지만, 온도, 빛, 그리고 게이트 바이어스 스트레스에 의한 문턱전압의 불안정성이 문제의 문제를 해결해야한다. 산화물 반도체의 문턱전압의 불안정성은 유전체와 채널층의 계면 혹은 채널에서의 charge trap, photo-generated carrier, ads-/desorption of molecular 등의 원인으로 보고되고 있어, 고신뢰성의 산화물 채널층을 성장하기 위한 노력이 이루어지고 있다. 최근, 산화물 트랜지스터의 다양한 조건에서의 문턱전압의 불안정성을 해결하기 위해 산화물의 주된 결함으로 일컬어지고 있는 산소결핍을 억제하기 위해 성장공정의 제어 그리고, 산소와의 높은 binding energy를 같은 Al, Hf, Si 등과 같은 원소를 첨가하여 향상된 소자의 특성이 보고되고 있지만, 줄어든 산소공공으로 인해 이동도가 저하되는 문제점이 야기되고 있다. 이러한 문제점을 해결하기 위해, 최근에는 Buried layer의 삽입 혹은 bi-channel 등과 같은 방안들이 제안되고 있다. 본 연구는 atomic layer deposition을 이용하여 AZO bureid layer가 적용된 ZnO 트랜지스터의 특성과 안정성에 대한 연구를 하였다. 다결정 ZnO 채널은 유전체와의 계면에 많은 interface trap density로 인해 positive gate bias stress에 의한 문턱전압의 불안정성을 보였지만, AZO층이 적용된 ZnO 트랜지스터는 줄어든 interface trap density로 인해 향산된 stability를 보였다.