• 전자공학회논문지
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• 제50권7호
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• pp.115-121
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• 2013

본 연구에서는 TiInZnO(TiIZO)를 채널층으로 하는 thin film transistors(TFTs)를 제작하였다. TiIZO 층은 InZnO(IZO)와 Ti target을 이용하여 RF-magnetron co-sputtering system 방식으로 상온에서 증착하였으며, 어떠한 열처리도 하지 않았다. Ti의 첨가가 어떠한 영항을 주는지 연구하기 위해 X-ray diffraction(XRD), X-ray photoelectron spectroscopy(XPS) 분석을 시행하였으며, 전기적인 특성을 측정하였다. Ti의 첨가는 Ti target의 rf power 변화에 따라 달리하였다. Ti의 첨가가 전류점멸비에 큰 영향을 주는 것을 확인하였고, 이것은 Ti의 산화력이 In과 Zn보다 뛰어나 산소결함자리의 형성을 억제하기 때문이다. Ti의 rf power가 40W일 때 가장 좋은 특성을 나타냈으며, 전류점멸비, 전자이동도, 문턱전압, subthreshold swing이 각각 $10^5$, 2.09 [$cm^2/V{\cdot}s$]. 2.2 [V], 0.492 [V/dec.]로 측정되었다.

• Journal of Information Display
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• 제12권1호
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• pp.47-50
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• 2011

Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.

• 한국전기전자재료학회논문지
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• 제24권9호
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• pp.693-696
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• 2011

Recently, amorphous oxide semiconductors (AOSs) based thin-film transistors (TFTs) have received considerable attention for application in the next generation displays industry. The research trends of AOSs based TFTs investigation have focused on the high device performance. The electrical properties of the TFTs are influenced by trap density. In particular, the threshold voltage ($V_{th}$) and subthreshold swing (SS) essentially depend on the semiconductor/gate-insulator interface trap. In this article, we investigated the effects of Ar plasma-treated $SiO_2$ insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide (a-IGZO) TFTs. We report on the improvement in interfacial characteristics between a-IGZO channel layer and gate insulator depending on Ar power in plasma process, since the change of treatment power could result in different plasma damage on the interface.

• Journal of the Korean Physical Society
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• 제73권9호
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• pp.1351-1355
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• 2018

The photocurrent characteristics of zinc-oxide (ZnO) thin-film transistors (TFTs) prepared using radio-frequency sputtering and spin-coating methods were investigated. Various characterization methods were used to compare the physical and the chemical properties of the sputtered and the spin-coated ZnO films. X-ray photoelectron spectroscopy was used to investigate the chemical composition and state of the ZnO films. The transmittance and the optical band gap were measured by using UV-vis spectrometry. The crystal structures of the prepared ZnO films were examined by using an X-ray diffractometer, and the surfaces of the films were investigated by using scanning electron microscopy. ZnO TFTs were prepared using both sputter and solution processes, both of which showed photocurrent characteristics when illuminated by light. The sputtered ZnO TFTs had a photoresponsivity of 3.08 mA/W under illumination with 405-nm light while the solution-processed ZnO TFTs had a photoresponsivity of 5.56 mA/W. This study provides useful information for the development of optoelectronics based on ZnO.

• 센서학회지
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• 제12권5호
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• pp.218-224
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• 2003

플라즈마, $H_2$와 $H_2$/플라즈마 공정에 의해 수소 처리시킨 n-채널 다결정실리콘 박막트랜지스터(TFT)를 제작하였다. 전압 바이어스 스트레스로 게이트 산화막에 유기된 감지 특성들을 분석하였다. 수소 처리시킨 소자에서 전기적 스트레스 조건에 의해 야기된 인자적 감지 특성들은 드레인전류, 문턱전압(Vth), 문턱전압 아래기울기(S), 그리고 최대 전달 컨덕턴스(Gm) 값을 측정하여 조사하였다. 분석 결과로서, 수소화 처리시킨 n-채널 다결정 실리콘 박막 트랜지스터에서 감지된 열화특성은 다결정실리콘/산화막의 계면과 다결정 실리콘의 그레인 경계에서 실리콘-수소(Si-H) 본드의 해리에 의한 현수 본드의 증가가 원인이 되었다. 게이트 산화막내 트랩의 생성은 채널 영역에서 게이트 산화막 속으로 핫 전자 주입에 의해 야기되었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• 전기전자학회논문지
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• 제26권3호
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• pp.500-505
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• 2022

본 연구에서는 새로운 구조의 dual gate tri-layer split channel 박막트랜지스터를 제작하였다. 전류 구동 능력을 향상시키기 위해 액티브 층의 양쪽에 게이트를 형성하였고 전하이동도를 증가시키기 위하여 액티브 층에서 채널이 형성되는 구간인 첫번째 층과 세번째 층에 전도성이 높은 ITO 층을 배치하였다. 추가적으로 분할 채널을 이용하여 채널의 series 저항을 낮추면서 분할한 채널의 측면에서도 accumulation을 유도하여 전하이동도를 향상시켰다. 기존의 single gate a-ITGZO 박막트랜지스터가 15 cm²/Vs의 전하이동도를 가지는 반면 dual gate tri-layer split channel 박막트랜지스터는 134 cm²/Vs의 높은 전하이동도를 가졌다.

• Transactions on Electrical and Electronic Materials
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• 제16권2호
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• pp.99-102
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• 2015

Thin film transistors (TFTs) with amorphous 2 wt% silicon-doped zinc tin oxide (a-2SZTO) channel layer were fabricated using an RF magnetron sputtering system, and the effect of post-annealing treatment time on the structural and electrical properties of a-2SZTO systems was investigated. It is well known that Si can effectively reduce the generation of oxygen vacancies. However, it is interesting to note that prolonged annealing could have a bad effect on the roughness of a-2SZTO systems, since the roughness of a-2SZTO thin films increases in proportion to the thermal annealing treatment time. Thermal annealing can control the electrical characteristics of amorphous oxide semiconductor (AOS) TFTs. It was observed herein that prolonged annealing treatment can cause bumpy roughness, which led to increase of the contact resistance between the electrode and channel. Thus, it was confirmed that deterioration of the electrical characteristics could occur due to prolonged annealing. The longer annealing time also decreased the field effect mobility. The a-2SZTO TFTs annealed at 500℃ for 2 hours displayed the mobility of 2.17 cm²/Vs. As the electrical characteristics of a-2SZTO annealed at a fixed temperature for long periods were deteriorated, careful optimization of the annealing conditions for a-2SZTO, in terms of time, should be carried out to achieve better performance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1453-1454
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• 2011

We have investigated the effect of silicon contents (0~0.4 molar ratios) on the performance of solution processed silicon-indium-zinc oxide (SIZO) thin-film transistors (TFTs). Despites its solution processed channel layer, low annealed temperature below $200^{\circ}C$ in air has been used for SIZO-TFTs. The $V_{th}$ is shifted from -4.04 to 5.15 V as increasing Si ratio in the SIZO-TFTs. The positive shift of $V_{th}$ as increasing Si contents in SIZO system indicates that Si suppresses the carrier generation in the active channel layer since $V_{th}$ is defined as the voltage required accumulating sufficient charge carriers to form a conductive channel path.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.163-168
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• 2014

Bottom gate thin-film transistors were fabricated using solution processed IGZO channel layers with various gallium composition ratios that were annealed on a hot plate. Increasing the gallium ratio from 0.1 to 0.6 induced a threshold voltage shift in the electrical characteristics, whereas the molar ratio of In:Zn was fixed to 1:1. Among the devices, the IGZO-TFTs with gallium ratios of 0.4 and 0.5 exhibited suitable switching characteristics with low off-current and low SS values. The IGZO-TFTs prepared from IGZO films with a gallium ratio of 0.4 showed a mobility, on/off current ratio, threshold voltage, and subthreshold swing value of $0.1135cm^2/V{\cdot}s$, ${\sim}10^6$, 0.8 V, and 0.69 V/dec, respectively. IGZO-TFTs annealed at $300^{\circ}C$, $350^{\circ}C$, and $400^{\circ}C$ were also fabricated. Annealing at lower temperatures induced a positive shift in the threshold voltage and produced inferior electrical properties.