• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.4
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• pp.400-406
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• 2024

Next-generation wide-bandgap semiconductors such as SiC, GaN, and Ga2O3 are being considered as potential replacements for current silicon-based power devices due to their high mobility, larger size, and production of high-quality wafers at a moderate cost. In this study, we investigate the gradual modulation of chemical composition in multi-stacked metal oxide semiconductor thin films to enhance the performance and bias stability of thin-film transistors (TFTs). It demonstrates that adjusting the Ga ratio in the indium gallium oxide (IGO) semiconductor allows for precise control over the threshold voltage and enhances device stability. Moreover, employing multiple deposition techniques addresses the inherent limitations of solution-processed amorphous oxide semiconductor TFTs by mitigating porosity induced by solvent evaporation. It is anticipated that solution-processed indium gallium oxide (IGO) semiconductors, with a Ga ratio exceeding 50%, can be utilized in the production of oxide semiconductors with wide band gaps. These materials hold promise for power electronic applications necessitating high voltage and current capabilities.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2329-2331
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• 1999

Metal oxide surge arrester were developed in the late 1970s, and were immediately adopted as significant breakthrough in over voltage protection of power system. Work was continued throughout the world on the design, development and application of metal oxide surge arrester. This paper describes the evaluating test and results of practical use for analyzing the performance of gapless metal oxide surge arresters under various type test.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1459-1461
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• 1998

This paper provides the results of analysis of lightening arrester failed in the field. XRD was used for qualitative analysis and SEM for microstructure analysis of zinc oxide (ZnO) block. The failure of lightening arrester might occur due to the following reasons: the uneven size of zinc oxide grains and cement layers. the re-crystallization of zinc oxide grains resulting from electrical stress around impurities, and the presence of too large pores($\simeq$ 50 ${\mu}m$).

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.257-263
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• 2006

New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.90-94
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• 2015

We stuidied liauid crystal alignment treatment using solution process for making thin oxide layer in liquid crystal display. It is the one of very effient and popular process in making thin oxide layer in electronical industrial fields. Particularly, this process has highly potential value in liquid crystal display industrial fields because it cause automatically induced alignment process without tranditional alignment process in liquid crystal alignment process. We made several different kinds of mol density solutions using strontium oxide solution. And those solutions were treated for solidification layers using annealing process for 2 hours. And we stuided pretilt angle properties of these alignment layers of strontium oxide for clarifying the relationship of liquid crystal molecules and thin strontium oxide layer. And we also tested the existence of strontium oxide thin layer on substrate using XPS measurement. We expected the hig gain of electro-optical properties in liquid crystal display using strontium oxide thin layer because it has high K property material than the other metal-based oxide layers. In this results, we measured 1.447 to 1.613 thresholds volts as 0.1 mol to 0.4 mol density in 0.1 mol density steps. This is significant better characteristics than conventional liquid crystal display as higher than 1.85 thresholds volts. And it make possible to making next-generation liquid crystal display which present low-power consumption and wide gray scale in liquid crystal display.

• ETRI Journal
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• v.21 no.3
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• pp.22-28
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• 1999

A new tapered TEOS oxide technique has been developed to use field oxide of the power integrated circuits. It provides better uniformity of less than 3 % and reproducibility. On-resistance of P-channel RESURE (REduced SURface Field) LDMOS transistors has been optimized and improved by using a novel simulation and tapered TEOS field oxide on the drift region of the devices. With the similar breakdown voltage, at $V_{gs}$=-0.5V, the specific on-resistance of the LDMOS with the tapered field oxide is about $31.5{\Omega}{\cdot}cm^2$, while that of the LDMOS with the conventional field oxide is about $57m{\Omega}{\cdot}cm^2$.

• Journal of the Korean Ceramic Society
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• v.37 no.2
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• pp.194-200
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• 2000

Sb-doped tin oxide films were deposited on Corning glass 1737 substrate by plasma enhanced chemical vapor deposition(PECVD) technique using a gas mixture of SnCl4/SbCl5/O2/Ar. The deposition behaviors of tin oxide films by PECVD were compared with those by thermal CVD, and effects of deposition temperature, r.f. power and Sb doping on the electrical properties of tin oxide films were investigated. PECVD technique largely increased the deposition rate and smoothed the surface of tin oxide films compared with thermal CVD. Electrical resistivity decreased with doping of Sb due to the increase of carrier concentration. However, large doping of Sb diminished carrier concentration and mobility due to the decrease of crystallinity, which resulted in the increase of electrical resistivity. As the deposition temperature and r.f. power increased, Cl content in the film decreased.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Journal of Power System Engineering
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• v.18 no.6
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• pp.7-12
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• 2014

The effect of various synthesis conditions in the fabrication of graphene using the exfoliation methods has been investigated. Graphite oxide and graphene fabricated by various synthesis conditions were identified by SEM and XRD. Graphite oxide was made from graphite by the chemical oxidation, and graphene was manufactured from graphite oxide by thermal exfoliation method. As a result, it is confirmed that graphite oxide was well formed from graphite, and the graphene could be obtained from graphite oxide. And it was found that the interlayer spacing between the graphene layers depended on the reaction time and particle size, regardless of the reaction temperature from $5^{\circ}C$ to $25^{\circ}C$.