References
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Integration of Power LDMOS into a Low-Voltage 0.5
${\mu>m$ BiCMOS Technology Tsui, P.G.Y.;Gilbert, P.V.;Sun, S.W. - Proceeding of ISPSD' 97 A Novel High-Frequency LDMOS Transistor Using an Extended Gate RESURF Technology Vestling, L.;Edhholm, B.;Olsson, J.;Tiensuu, S.;Soderbrag, A.
- NEC Res. & Develop. v.35 no.4 Development of Process for Low On-Resistance Vertical Power MOSFETs Kobayashi, K.;Ninomiya, Y.;Takahashi, M.;Maruoka, M.
- ETRI Journal v.20 no.1 Integration of 5-V CMOS and High-Voltage Devices for Display Driver Applications Kim, Jong-Dae; Park, Mun-Yang;Kang, Jin-Yeong;Lee, Sang-Yong;Koo, Jin-Gun;Nam, Kee-Soo
- High Voltage Thin Layer Devices (RESURF Devices) Appels, J.A.;Vaes, H.M.J.
- Semiconductor Power Devices Ghandhi, S.K.
- IEEE EDL v.EDL-16 Breakdown Voltage Enhancement of the p-n Junction by Self- Aligned Double Diffusion Process through a Tapered SiO2 Implant Mask Kim, H.S.;Kim, S.D.;Han, M.K.;Yoon, S.N.;Choi, Y.I.
- IEEE Trans. Electron Devices v.ED-25 Tapered Windows in Phosphorus-Doped SiO2 by Ion Implantation North, J.C.;McGahan, T.E.;Rice, D.W.;Adams, A.C.
- IEEE EDL v.EDL-1 Graded Etching of Thermal Oxide with Various Angles Using Silica Film Choi, Y.I.;Kwon, Y.S.;Kim, C.K.
- Solid-State Electron v.41 no.8 Boron out Diffusion from Si Substrates in Various Ambients Suzuki, K.;Yamawaki, H.;Tada, Y.
- Japan. J. of Appl. Phys. v.3 no.7 Redistribution of Diffused Boron in Silicon by Thermal Oxidation Kato, T.;Nishi, Y.
- DIOS AND DESSIS User's Manual ISE
- Proceeding of ISPSD '98 A Novel p-channel SOI LDMOS Transistor with Tapered Field Oxides Kim, Jong-Dae;Kim, Sang-Gi;Roh, Tae-Moon;Koo, Jin-Gun;Nam, Kee-Soo