• 한국전기전자재료학회논문지
• /
• 제24권9호
• /
• pp.693-696
• /
• 2011

Recently, amorphous oxide semiconductors (AOSs) based thin-film transistors (TFTs) have received considerable attention for application in the next generation displays industry. The research trends of AOSs based TFTs investigation have focused on the high device performance. The electrical properties of the TFTs are influenced by trap density. In particular, the threshold voltage ($V_{th}$) and subthreshold swing (SS) essentially depend on the semiconductor/gate-insulator interface trap. In this article, we investigated the effects of Ar plasma-treated $SiO_2$ insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide (a-IGZO) TFTs. We report on the improvement in interfacial characteristics between a-IGZO channel layer and gate insulator depending on Ar power in plasma process, since the change of treatment power could result in different plasma damage on the interface.

• 센서학회지
• /
• 제19권6호
• /
• pp.483-489
• /
• 2010

Display quality depends on panel temperatures. To compensate it, temperature sensor was integrated on the panel. The conventional temperature sensor integrated on the panel needs external reference resistor. Since the resistance of external resistor can vary according to the variation of the environment temperature, the conventional temperature sensor can make error in temperature sensing. The environmental temperatures can change by the back light unit, driving circuits or chips. In this paper, we proposed a integrated temperature sensor on display panel which does not need external reference resister. Instead of external reference resistor, we used two materials which have different temperature coefficient in resistivity. They are connected serially and the output voltage was measured at the point of connection with the applied voltage to both ends. The proposed sensor was fabricated with indium tin oxide(ITO), and Mo metal electrode temperature sensor which were connected serially. We verified the temperature senor by the measurements of sensitivity, lineality, hysteresis, repeatability, stability, and accuracy.

• 반도체디스플레이기술학회지
• /
• 제18권1호
• /
• pp.1-4
• /
• 2019

Reactive sputtering is widely used because of its high deposition rate and high step coverage. The deposition layer is often affected by target poisoning because the target conditions are changed, as well, by reactive gases during the initial stage of sputtering process. The reactive gas affects the deposition rate and process stability (target poisoning), and it also leads unintended oxide interlayer formation. Although the target poisoning mechanism has been well known, little attention has been paid on understanding the interlayer formation during the reactive sputtering. In this research, we studied the interlayer formation during the reactive sputtering. A DC magnetron sputtering process is carried out to deposit an aluminum oxide film on a silicon wafer. From the real-time process monitoring and material analysis, the target poisoning phenomena changes the reactive gas balance at the initial stage, and affects the interlayer formation during the reactive sputtering process.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 1994년도 추계 학술발표 강연 및 논문 개요집
• /
• pp.89-89
• /
• 1994

• E2M - 전기 전자와 첨단 소재
• /
• 제16권9호
• /
• pp.62.3-63
• /
• 2003

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2003년도 추계학술대회 논문요약집
• /
• pp.177-177
• /
• 2003

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 1994년도 제7회 학술발표회 및 한·일 CVD 심포지움 논문개요집
• /
• pp.79-79
• /
• 1994

• Journal of Electrical Engineering and Technology
• /
• 제6권2호
• /
• pp.280-283
• /
• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• 한국전기전자재료학회논문지
• /
• 제14권7호
• /
• pp.533-538
• /
• 2001

The barrier height is found to increase from 0.25 to 0.690 eV for Schottky contacts on n-InGaAs using deposition of Ag on a substrate cooled to 77K(LT). Surface analysis leads to an interface model for the LT diode in which there are oxide compounds of In:O and As:O between the metal and semiconductor, leading to behavior as a metal-insulator-semiconductor diode. The metal film deposited t LT has a finer and more uniform structure, as revealed by scanning electron microscopy and in situ metal layer resistance measurement. This increased uniformity is an additional reason for the barrier height improvement. In contrast, the diodes formed at room temperature exhibit poorer performance due to an unpassivated surface and non-uniform metal coverage on a microscopic level.

• 반도체디스플레이기술학회지
• /
• 제3권2호
• /
• pp.11-15
• /
• 2004

Scales, accumulated on some parts of semiconductor equipments such as sputters and CVD during the device fabrication processes, often lower the lifetime of the equipments and production yields. Thus, many equipment parts have be cleaned regularly. In this study, an attempt to establish an effective process to remove scales on the sidewall of collimators located inside the chamber of the sputter was made. The EDX analysis revealed that the scales were composed of Ti and TiN with the columnar structure. Through the trial-and-error experiments, it was found that the etching in the $HNO_3$:$H_2SO_4$:$H_2O$=4:2:4 solution for 5.5 hrs at $67^{\circ}C$, after the oxide removal in the HF solution, and the heat-treatment at $700^{\circ}C$ for 1 min., was the most effective process for the scale removal.