• 제목/요약/키워드: Oxide Semiconductor

검색결과 1,419건 처리시간 0.024초

Pulsed-DC 스퍼터링에서 Reverse Pulse Time에 따른 AZO 박막의 특성 변화에 관한 연구 (A Study on the Dependency of Pulsed-DC Sputtered Aluminum-doped Zinc Oxide Thin Films on the Reverse Pulse Time)

  • 류형석;조진건;권상직;조의식
    • 반도체디스플레이기술학회지
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    • 제17권4호
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    • pp.32-36
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    • 2018
  • For various oxygen($O_2$) to argon(Ar) gas ratio, aluminum-doped zinc oxide(AZO) films were deposited for 3 min at different duty ratio by changing reverse pulse times. As the duty ratio increased, the thickness of the AZO film decreased and the sheet resistance increased. It can be concluded that When sputtering AZO Thin film, oxygen interfered with sputtering. When the reverse time was increased, the thickness of AZO was proportional to the real sputtering time and decreased. From the optical transmittance and sheet resistance, it was possible to obtain a higher figure of merits of AZO at a lower reverse pulse time. Even at the short reversed pulse time, it can be concluded that the accumulated charges on the AZO target are completely cleared. At a lower reverse pulse time, pulsed-DC sputtering of AZO is expected to be used instead of DC sputtering in the deposition of transparent conductive oxide(TCO) films without any degradation in thickness and structural/electrical characteristics.

DC Characteristics of P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with $Si_{0.88}Ge_{0.12}(C)$ Heterostructure Channel

  • Choi, Sang-Sik;Yang, Hyun-Duk;Han, Tae-Hyun;Cho, Deok-Ho;Kim, Jea-Yeon;Shim, Kyu-Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권2호
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    • pp.106-113
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    • 2006
  • Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

능동층 구조에 따른 비정질산화물반도체 박막트랜지스터의 특성 (The Characteristics of Amorphous-Oxide-Semiconductor Thin-Film-Transistors According to the Active-Layer Structure)

  • 이호년
    • 한국산학기술학회논문지
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    • 제10권7호
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    • pp.1489-1496
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    • 2009
  • 비정질 인듐-갈륨-아연 산화물 박막트랜지스터를 모델링 하여서, 능동층의 구조, 두께, 평형상태의 전자밀도에 대응하는 박막트랜지스터의 특성을 연구하였다. 단일 능동층 박막트랜지스터의 경우, 능동층이 얇을 때 높은 전계효과이동도를 보였다. 문턱전압의 절대값은 능동층의 두께가 20 nm일 때 최저치를 보였으며, 문턱전압이하 기울기는 두께에 대한 의존성을 보이지 않았다. 복층구조 능동층의 경우, 하부의 능동층이 높은 평형상태 전자밀도를 가질 때보다 우수한 스위칭 특성을 보였다. 이 경우에도 능동층의 두께가 얇을 때에 높은 전계효과 이동도를 보였다. 높은 평형상태 전자밀도의 능동층의 두께를 증가시키면 문턱전압은 음의 방향으로 이동하였다. 문턱전압이하 기울기는 능동층의 구조에 대하여 특별한 의존성을 보이지 않았다. 이상과 같은 데이터는 산화물반도체 박막트랜지스터 능동층의 구조, 두께, 도핑비율을 최적화함에 효과적으로 사용될 것으로 기대된다.

박막 MOS 구조의 고정표면전하에 관한 연구 (A Study of fixed oxide charge in thin flim MOS structure)

  • 유석빈;김상용;서용진;장의구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1989년도 하계종합학술대회 논문집
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    • pp.377-379
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    • 1989
  • Very thin gate oxide(100-300A) MOS capacitor has been fabricated. The effect of series resistance must be calculated and the exact metal-semiconductor work function difference should be obtained to get the fixed oxide charge density exisiting in oxide. Dilute oxidation make sagy to control oxide thickness and reduce fixed oxide charge density. In case of dilute oxidation, fixed oxide charge density depends on oxidation time. If oxide is very thin, the annealing effect is ignored.

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Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory

  • Kim, Seunghyun;Kwon, Dae Woong;Lee, Sang-Ho;Park, Sang-Ku;Kim, Youngmin;Kim, Hyungmin;Kim, Young Goan;Cho, Seongjae;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권2호
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    • pp.167-173
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    • 2017
  • In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

(-201)면 산화갈륨 단결정 기판 미세 결함 분석 (Characterizations of Microscopic Defect Distribution on (-201) Ga2O3 Single Crystal Substrates)

  • 최미희;신윤지;조성호;정운현;정성민;배시영
    • 한국전기전자재료학회논문지
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    • 제35권5호
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    • pp.504-508
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    • 2022
  • Single crystal gallium oxide (Ga2O3) has been an emerging material for power semiconductor applications. However, the defect distribution of Ga2O3 substrates needs to be carefully characterized to improve crystal quality during crystal growth. We analyzed the type and the distribution of defects on commercial (-201) Ga2O3 substrates to get a basic standard prior to growing Ga2O3 crystals. Etch pit technique was employed to expose the type of defects on the Ga2O3 substrates. Synchrotron white beam X-ray topography was also utilized to observe the defect distribution by a nondestructive manner. We expect that the observation of defect distribution with three-dimensional geometry will also be useful for other crystal planes of Ga2O3 single crystals.

3- Transistor Cell OTP ROM Array Using Standard CMOS Gate-Oxide Antifuse

  • Kim, Jin-Bong;Lee, Kwy-Ro
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제3권4호
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    • pp.205-210
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    • 2003
  • A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

칼코겐화물과 산화물 이종구조의 각도분해능 광전자분광 연구 (Angle-resolved photoemission spectrscopy for chalcogenide and oxide heterostructures)

  • 장영준
    • 진공이야기
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    • 제5권2호
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    • pp.10-17
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    • 2018
  • Chalcogenide and oxide heterostructures have been studied as a next-generation electronic materials, due to their interesting electronic properties, such as direct bandgap semiconductor, ferroelectricity, ferromagnetism, superconductivity, charge-density waves, and metal-insulator transition, and their modification near heterointerfaces, so called, electronic reconstruction. An angle-resolved photoemission spectroscopy (ARPES) is a powerful technique to unveil such novel electronic phases in detail, especially combined with high quality thin film preparation methods, such as, molecular beam epitaxy and pulsed laser deposition. In this article, the recent ARPES results in chalcogenide and oxide thin films will be introduced.