• Journal of the Korean Society for Precision Engineering
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• v.13 no.11
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• pp.46-56
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• 1996

Planarization technique is rapidly recognized as a critical step in chip fabrication due to the increase in wiring density and the trend towards a three dimensional structure. Global planarity requires the preferential removal of the projecting features. Also, the several materials i.e. Si semiconductor, oxide dielectric and sluminum interconnect on the chip, should be removed simultaneously in order to produce a planar surface. This research has investihgated the development of the chemical mechanical polishing(CMP) machine with uniform pressure and velocity mechanism, and the pad insensitive to pattern topography named hard grooved(HG) pad for global planarization. Finally, a successful result of uniformity less than 5% standard deviation in residual oxide film and planarity less than 15nm in residual step height of 4 inch device wafer, is achieved.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.3
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• pp.175-184
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• 2001

In this study, the improved throughput and stability in device fabrication could be obtained by applying CMP process to STi structue in 0.18 um semiconductor device. To employ the CMP process in STI structure, the Reverse Moat Process used to be added after STI Fill, as a result, the process became more complex and the defect were seriously increased than they had been,. Removal rate of each thin film in STI CMP was not uniform, so, the device must have been affected. That is, in case of excessive CMP, the damage on the active area was occurred, and in the case of insufficient CMP nitride remaining was happened on that area. Both of them deteriorated device characteristics. As a solution to these problems, the development of slurry having high removal rate and high oxide to nitride selectivity has been studied. The process using this slurry afford low defect levels, improved yield, and a simplified process flow. In this study, we evaluated the 'High Selectivity Slurry' to do a global planarization without reverse moat step, and also we evaluated EPD(Eend Point Detection) system with which 'in-situ end point detection' is possible.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.163-166
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• 2006

The dishing and the erosion were evaluated on the tungsten CMP process with conventional and new developed slurry. The tungsten thin film was polished by orbital polishing equipment. Commercial pattern wafer was used for the evaluation. Both slurries were pre tested on the oxide region on the wafer surface and the removal rate was not different very much. At the pattern density examination, the erosion performance was increased at all processing condition due to the reduction of thickness loss in new slurry. However, the dishing thickness was not remarkably changed at high pattern density despite of the improvement at low pattern density. At the large pad area, the reduction of dishing thickness was clearly found at new tungsten slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.378-381
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• 2003

The chemical mechanical polishing (CMP) has been widely accepted for the global planarization of multi-layer structures in semiconductor manufacturing However, cost of ownership (COO) and cost of consumables (COC) were relatively increased because of expensive slurry. In this paper, the effects of different slurry composition on the oxide CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity. We prepared the various kinds of slurry. In order to save the costs of slurry, the original slurry was diluted by de-ionized water (DIW). And then, alunima abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.441-446
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• 2003

The chemical mechanical polishing (CMP) process is now widely employed in the ultra large scale integrated (ULSI) semiconductor fabrication. Especially, shallow trench isolation (STI) has become a key isolation scheme for sub-0.13/0.10${\mu}{\textrm}{m}$ CMOS technology. The most important issues of STI-CMP is to decrease the various defects such as nitride residue, dishing, and tom oxide. To solve these problems, in this paper, we studied the planarization characteristics using slurry additive with the high selectivity between $SiO_2$ and $Si_3$$N_4$ films for the purpose of process simplification and in-situ end point detection. As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also, we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of STI-CMP process.

• Journal of IKEEE
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• v.23 no.4
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• pp.1175-1181
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• 2019

In this paper, we have studied the chemical mechanical polishing(CMP) characteristics of mixed abrasive silica slurry(MAS) retreated by adding of manganese oxide(MnO₂) abrasives within 1:10 diluted silica slurry. A slurry designed for optimal performance should produce high removal rates, acceptable polishing selectivity with respect to the underlying layer, low surface defects after polishing, and good slurry stability. The polishing performances of MnO₂ abrasive-added MAS are evaluated with respect to their particle size distribution, surface morphology, and CMP performances such as removal rate and non-uniformity. As an experimental result, we obtained the comparable slurry characteristics compared to original silica slurry in the view-point of high removal rate and low non-uniformity. Therefore, our proposed MnO₂-MAS can be useful to save on the high cost of slurry consumption since we used a 1:10 diluted silica slurry.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.2 no.4
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• pp.17-24
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• 2003

Chemical mechanical polishing(CMP) has been applied for planarization of topography after patterning process in semiconductor fabrication process. Tungsten CMP is necessary to build up interconnects of semiconductor device. But the tungsten dishing and the oxide erosion defects appear at end-point during tungsten CMP. It has been known that the generation of dishing and erosion is based on the over-polishing time, which is determined by pattern selectivity. Fixed abrasive pad takes advantage of decreasing the defects resulting flam reducing pattern selectivity because of the lower abrasive concentration. The manufacturing technique of fixed abrasive pad using hydrophilic polymers is introduced in this paper. For application to tungsten CMP, chemicals composed of oxidizer, catalyst, and acid were developed. In comparison of the general pad and slurry for tungsten CMP, the fixed abrasive pad and the chemicals resulted in appropriate performance in point of removal rate, uniformity, material selectivity and roughness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.335-338
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• 2003

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-layer dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding $1\;{\mu}m$ in size, which could cause micro-scratch on the wafer surface. In this paper, we have studied aging effect the of CMP sin as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Tribology and Lubricants
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• v.39 no.2
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• pp.72-75
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• 2023

Silicon carbide (SiC) is used as a substrate material for power semiconductors; however, SiC chemical mechanical polishing (CMP) requires considerable time owing to its chemical stability and high hardness. Therefore, researchers are attempting to increase the material removal rate (MRR) of SiC CMP using various methods. Mixed-abrasive CMP (MAS CMP) is one method of increasing the material removal efficiency of CMP by mixing two or more particles. The aim of this research is to study the mathematical modeling of the MRR of MAS CMP of SiC with SiO₂ and TiO₂ particles. With a total particle concentration of 32 wt, using 80-nm SiO₂ particles and 25-nm TiO₂ particles maximizes the MRR at 8 wt of the TiO₂ particle concentration. In the case of 5 nm TiO₂ particles, the MRR tends to increase with an increase in TiO₂ concentration. In the case of particle size 10-25 nm TiO₂, as the particle concentration increases, the MRR increases to a certain level and then decreases again. TiO₂ particles of 25 nm or more continuously decreased MRR as the particle concentration increased. In the model proposed in this study, the MRR of MAS CMP of SiC increases linearly with changes in pressure and relative speed, which shows the same result as the Preston's equation. These results can contribute to the future design of MAS; however, the model needs to be verified and improved in future experiments.