• Title/Summary/Keyword: Organic gate insulator

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Fabrication and Characterization of Gate Insulator Thin Films prepared by Plasma Polymerization (플라즈마 중합법에 의한 게이트 절연박막의 제작 및 특성)

  • Son, Young-Do;Hwang, Myung-Whan;Lim, Jae-Sung;Shin, Paik-Kyun
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.25 no.12
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    • pp.48-53
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    • 2011
  • Polymer thin films were prepared by capacitively coupled plasma polymerization process for application of gate insulator. The polymer thin films revealed to form polymer layers with original properties of the monomer. Among the plasma polymer thin films, the styrene polymer having large number of phenyl sites revealed higher dielectric constant of k=3.7 than that of conventional polymer. The plasma polymerized styrene thin film revealed no hysteresis characteristics and low leakage current density of $1{\times}10^{-8}[Acm^{-2}]$ at field strength of $1[MVcm^{-1}]$, which measured by I-V and C-V measurements using MIM and MIS devices.

Low-Temperature Processable Polyimide Gate Insulator and Hybridization Approach for High Performance Pentacene Thin Film Transistor

  • Ahn, Taek;Kim, Jin-Woo;Yi, Mi-Hye
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.871-874
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    • 2007
  • We have synthesized a novel fully soluble and low-temperature processable polyimide gate insulator (KSPI) through one-step condensation polymerization. For the preparation of KSPI, 5- (2,5-dioxytetrahydrofuryl)-3-methly-3-cyclohexene- 1,2-dicarboxylic anhydride (DOCDA) and 4,4- diaminodiphenylmethane (MDA) were used as monomers and fully imidized KSPI was completely soluble in organic solvents like ${\gamma}-butyrolactone$ and 2-butoxyethanol, etc.

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Low-Voltage, Room temperature Fabricated ZnO Thin Film Transistor using High-K $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ Gate Insulator (고유전 $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ 게이트 절연막을 이용한 저전압 구동 상온공정 ZnO 박막트랜지스터)

  • Cho, Nam-Gyu;Kim, Dong-Hun;Kim, Kyoung-Sun;Kim, Ho-Gi;Kim, Il-Doo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.11a
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    • pp.96-96
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    • 2007
  • Low voltage organic TFTs (OTFTs) and ZnO based TFTs (<5V), utilizing room temperature deposited $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin films were recently reported, pointing to high-k gate insulators as a promising route for realizing low voltage operating flexible electronics. $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin film is one of the most promising materials for gate insulator because of its large dielectric constant (~60) at room temperature. However their tendency to suffer from relatively high leakage current at low electric field (>0.3MV/cm) hinder the application of BZN thin films for gate insulator. In order to improve leakage current characteristics of BZN thin film, we mixed 30mol% MgO with 70mol% BZN and their dielectric and electric properties were characterized. We fabricated field-effect transistors with transparent oxide semiconductor ZnO serving as the electron channel and high-k $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ as the gate insulator. The devices exhibited low operation voltages (<4V) due to high capacitance of the $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ dielectric.

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Effect of Characteristic of the Organic Memory Devices by the Number of CdSe/ZnS Nanoparicles Per Unit Area Changes

  • Kim, Jin-U;Lee, Tae-Ho;No, Yong-Han
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.388-388
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    • 2013
  • 현대 사회에서 고집적 및 고성능의 전자소자의 필요성은 지속적으로 요구되고 있으며, 투명하거나 플렉서블한 특성의 필요성에 따라 이에 대한 기술개발이 이루어지고 있다. 특히, 이러한 특성을 만족하면서 대면적화 및 저온 공정의 특성을 지니는 유기물 반도체가 주목받고 있고, 이를 이용하여 OLED (Organic Light Emitting Diode), OTFT (Organic Thin Film Transistor)와 같은 다양한 유기물 반도체 소자가 개발되고 있다. 대표적인 예로는이 있다. 유기물 반도체 소자의 특성을 이용한 메모리 소자 또한 연구 및 개발이 지속되고 있으며, 유연성과 낮은 공정가격 등의 특성을 가지는 나노 입자들이 기존 Floating Gate의 대체물로 각광받고 있다. 본 논문에서는 MIS (Metal/Insulator/Semiconductor) 구조를 제작하고, Insulator 내부에Core/Shell 구조를 가지는 CdSe/ZnS 나노 입자를 부착하여 메모리 소자의 특성 확인 및 단위 면적당 개수에 따른 특성 변화를 확인하고자 하였다. 합성된 PVP (Poly 4-Vinyl Phenol)를 Insulator 층으로 사용하였으며 단위 면적당 나노 입자의 개수를 조절하여 제작된 MIS 소자를 Capacitance versus Voltage (C-V) 측정을 통하여 변화특성을 확인하였다.

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Hysteresis Behavior in Pentacene Organic Thin-film Transistors

  • So, Myeong-Seob;Suh, Min-Chul;Koo, Jae-Bon;Choi, Byoung-Deog;Choi, Dae-Chul;Lee, Hun-Jung;Mo, Yeon-Gon;Chung, Ho-Kyoon
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.1364-1369
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    • 2005
  • In this paper, we have identified the mechanism of C-V hysteresis behavior often observed in pentacene organic thin-film transistors (OTFTs). The capacitance-voltage (C-V) characteristics were measured for pentacene OTFTs fabricated on glass substrates with MoW as gate/source/drain electrode and TEOS $SiO_2$ as gate insulator. The measurements were made at room temperature and elevated temperatures. From the room temperature measurements, we found that the hysteresis behavior was caused by hole injection into the gate insulator from the pentacene semiconductor for large negative gate voltages, resulting in the negative flat-band voltage shift. However electron injection was observed only at elevated temperatures

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A STUDY ON THE ELECTRICAL CHARACTERISTICS IMPROVEMENTS OF PENTACENE-BASED ORGANIC THIN FILM TRANSISTORS (Pentacene을 이용한 유기 TFT의 전기적 특성 향상에 관한 연구)

  • Lee, Jong-Hyuk;Park, Jae-Hoon;Ryu, Se-Won;Kim, Hyung-Joon;Choi, Jong-Sun
    • Proceedings of the KIEE Conference
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    • 2001.07c
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    • pp.1515-1517
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    • 2001
  • In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces have been interested. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-6}$ Torr and at a deposition rate of 0.3$\AA$/sec. Aluminium and gold were used for gate and source/drain electrodes. before pentacene is deposited on the insulator, the gate dielectric surfaces of two samples were rubbed with lateral and perpendicular to direction of the channel length respectively.

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Comparative Analysis on Positive Bias Stress-Induced Instability under High VGS/Low VDS and Low VGS/High VDS in Amorphous InGaZnO Thin-Film Transistors

  • Kang, Hara;Jang, Jun Tae;Kim, Jonghwa;Choi, Sung-Jin;Kim, Dong Myong;Kim, Dae Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.5
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    • pp.519-525
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    • 2015
  • Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

Properties of Organic PMMA Gate Insulator Film at Various Concentration and Film Thickness (PMMA 유기 게이트 절연막의 농도와 두께에 따른 특성)

  • Yoo, Byung-Chul;Gong, Su-Cheol;Shin, Ik-Sub;Shin, Sang-Bea;Lee, Hak-Min;Park, Hyung-Ho;Jeon, Hyung-Tag;Chang, Young-Chul;Chang, Ho-Jung
    • Journal of the Semiconductor & Display Technology
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    • v.6 no.4
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    • pp.69-73
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    • 2007
  • The MIM(metal-insulator-metal) capacitors with the Al/PMMA/ITO/Glass structures were manufactured according to various PMMA concentration of 1, 2, 4, 6, 8 wt%. The lowest leakage current and the largest capacitance were found to be 2.3 pA and 1.2 nF, respectively, for the device with 2 wt% PMMA concentration. The measured capacitance of the devices was almost same values with the calculated one. The optimum film thickness was obtained at the value of 48 nm, showing that the capacitance and leakage current were 1.92 nF, 0.3 pA at 2 wt%, respectively. From this experiment, the PMMA gate insulator films can be applicable to the organic thin film transistors.

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Electrical Properties of Organic PVA Gate Insulator Film on ITO/Glass Substrates (ITO/glass 기판위에 제작된 Cross linked PVA 유기 게이트 절연막의 전기적 특성)

  • Choi, Jin-Eun;Gong, Su-Cheol;Jeon, Hyeong-Tag;Park, Hyung-Ho;Chang, Ho-Jung
    • Journal of the Semiconductor & Display Technology
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    • v.9 no.4
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    • pp.1-5
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    • 2010
  • The PVA (poly-vinyl alcohol) insulators were spun coated onto ITO coated glass substrates with the capacitors of Glass/ITO/PVA/Al structure. The effects of PVA concentrations (3.0, 4.0 and 5.0 wt%) on the morphology and electrical properties of the films were investigated. As the concentration of PVA increased from 3.0 to 5.0 wt%, the leakage current of device decreased from 17.1 to 0.23 pA. From the AFM measurement, the RMS value decreased with increasing PVA concentration, showing the improvement of insulator film roughness. The capacitances of the films with PVA concentrations of 4.0 and 5.0 wt% were about 28.1 and 24.2 nF, respectively. The lowest leakage current of 1.77 PA was obtained at the film thickness of 117.5 nm for the device with fixed PVA concentration of 5.0 wt%.