• ETRI Journal
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• v.36 no.3
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• pp.367-373
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• 2014

With high bandwidth, low interference, and low power consumption, optical network-on-chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path-setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non-blocking $6{\times}6$ optical router is designed to support the new method. The simulation results show the new path-setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot-I, and hotspot-II traffic patterns, respectively. The end-to-end delay performance is also improved.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.89-103
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.120-136
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.104-119
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.83-93
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• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.412-419
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• 2001

In accordance with the PON(passive optical network) could be setup, effective connections with light sources, optical detectors, and optical fibers are the best sensitive points to represent the efficiency of network. Therefore, in this paper we designed and fabricated optical transceiver connection chip that was consisted of channel waveguide, Y-branch, and CWDM on the 2" BK7 glass substrate. This chip can be used for 1.31/1.55${\mu}{\textrm}{m}$ CWDM network and 1.55${\mu}{\textrm}{m}$ region dense WDM network.work.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.40-48
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• 2015

An optical network-on-chip(ONoC) architecture is emerging as a new paradigm for solving on-chip communication bottleneck. Recent studies on ONoC have been focusing on supporting the parallel transmission and avoiding path collisions using wavelength division multiplexing(WDM). However, since the maximum number of wavelengths, which a single waveguide can accommodate is limited by crosstalk and insertion loss. Therefore previous WDM studies based on incrementing the number of different wavelengths according to the number of nodes would be infeasible due to the implementation complexity. To solve such problems, we combined time division multiplexing(TDM) and wavelength-routed ONoC, along with an optimized channel allocation algorithm, which can minimize the number of extra wavelength channels and latency caused by combining TDM scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.25-32
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• 2009

Recently, research for Network-on-chip(NoC) is progressing. However, due to the increase of system complexity and demand on high performance, conventional copper-based electrical interconnect would be faced with the design limitation of performance, power, and bandwidth. As an alternative to these problems, combined use of Electrical Interconnects(EIs) and Optical Interconnects(OIs) has been introduced. In this paper we propose efficient routing optimization strategy and hybrid switch architecture, which use OIs for critical path and EIs for non-critical path. The proposed method shows up to 25% performance improvement and 38% power reduction.