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http://dx.doi.org/10.4218/etrij.14.0113.0675

New Path-Setup Method for Optical Network-on-Chip  

Gu, Huaxi (State Key Laboratory of ISN, Shenzhen CU-Xidian Joint Center, Xidian University)
Gao, Kai (State Key Laboratory of ISN, Shenzhen CU-Xidian Joint Center, Xidian University)
Wang, Zhengyu (State Key Laboratory of ISN, Shenzhen CU-Xidian Joint Center, Xidian University)
Yang, Yintang (Institutes of Microelectronics, Xidian University)
Yu, Xiaoshan (State Key Laboratory of ISN, Shenzhen CU-Xidian Joint Center, Xidian University)
Publication Information
ETRI Journal / v.36, no.3, 2014 , pp. 367-373 More about this Journal
Abstract
With high bandwidth, low interference, and low power consumption, optical network-on-chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path-setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non-blocking $6{\times}6$ optical router is designed to support the new method. The simulation results show the new path-setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot-I, and hotspot-II traffic patterns, respectively. The end-to-end delay performance is also improved.
Keywords
Optical network-on-chip; ONoC; path-setup method; optical router; network performance;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 C. Sun et al., "DSENT-A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling," IEEE/ACM Int. NoCS, Copenhagen, Denmark, May 9-11, 2012, pp. 201-210.
2 B.G. Lee et al., "High-Performance Modulators and Switches for Silicon Photonic Networks-on-Chip," IEEE J. Sel. Topics Quantum Electron., vol. 16, no. 1, Jan. - Feb. 2010, pp. 6-22.   DOI   ScienceOn
3 W.M.J. Green et al., "Ultra-Compact, Low RF Power, 10 Gb/s Silicon Mach-Zehnder Modulator," Opt. Exp., vol. 15, no. 25, Dec. 2007, pp. 17106-17113.   DOI
4 C. Xu et al., "High-Frequency Modeling and Optimization of E/O Response and Reflection Characteristics of 40 Gb/s EML Module for Optical Transmitters," ETRI J., vol. 34, no. 3, June 2012, pp. 361-368.   DOI
5 Y.H. Kwon et al., "Fabrication of 40 Gb/s Front-End Optical Receivers Using Spot-Size Converter Integrated Waveguide Photodiodes," ETRI J., vol. 27, no. 5, Oct. 2005, pp. 484-490.   DOI   ScienceOn
6 A. Shacham, K. Bergman, and L.P. Carloni, "Photonic Networkson-Chip for Future Generations of Chip Multiprocessors," IEEE Trans. Comput., vol. 57, no. 9, Sept. 2008, pp. 1246-1260.   DOI   ScienceOn
7 K.H. Mo et al., "A Hierarchical Hybrid Optical-Electronic Network-on-Chip," IEEE VLSI, Lixouri, Greece, July 5-7, 2010, pp. 327-332.
8 H. Gu, J. Xu, and W. Zhang, "A Low-Power Fat Tree-Based Optical Network-on-Chip for Multiprocessor System-on-Chip," Proc. DATE, Nice, France, Apr. 20-24, 2009, pp. 3-8.
9 Y. Ye et al., "3D Optical Networks-on-Chip (NoC) for Multiprocessor Systems-on-Chip (MPSoC)," IEEE Int. Conf. 3D Syst. Integr., San Francisco, CA, USA, Sept. 28-30, 2009, pp.1-6.
10 G. Hendry et al., "Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing," Int. Conf. High Performance Comput., Netw., Storage Anal., New Orleans, LA, USA, 2010, pp. 1-12.
11 L. Zhang et al., "Circuit-Switched on-Chip Photonic Interconnection Network," IEEE Int. Conf. Group IV Photon., San Diego, CA, USA, Aug. 29-31, 2012, pp. 282-284.
12 N. Sherwood-Droz et al., "Optical 4${\times}$4 Hitless Slicon Router for Optical Networks-on-Chip (NoC)," Opt. Exp., vol. 16, no. 20, Sept. 29, 2008, pp. 15915-15922.   DOI
13 A.B. Kahng et al., "ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration," Conf. DATE, Nice, France, Apr. 20-24, 2009, pp. 423-428.
14 Z. Li et al., ''Device Modeling and System Simulation of Nanophotonic on-Chip Networks for Reliability, Power and Performance,'' Proc. DAC, New York, USA, June 2011, pp. 735- 740.
15 G. Chen et al., "Predictions of CMOS Compatible on-Chip Optical Interconnect," ACM/IEEE Int. Workshop Syst. Level Interconnect Prediction, San Francisco, USA, Apr. 2005, pp. 13-20.
16 K.C. Cadien et al., "Challenges for on-Chip Optical Interconnects," SPIE 5730, Optoelectronic Integr. Silicon II, Mar. 14, 2005, pp. 133-143.
17 M. Stucchi et al., "Benchmarking on-Chip Optical Against Electrical Interconnect for High-Performance Applications," IEEE IITC/MAM, Dresden, Germany, May 2011, pp. 1-3.
18 Q. Li et al., "A Temperature-Insensitive Third-Order Coupled-Resonator Filter for on-Chip Terabit/s Optical Interconnects," IEEE Photon. Technol. Lett., vol. 22, no. 23, Dec. 1, 2010, pp. 1768-1770.   DOI   ScienceOn