• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.155-165
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• 1994

An analog neural network circuit of rhigh density integration is introduced. It's prototype chip is designed in 3 by 3 mm2 die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by cascading several chips. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.46-51
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• 1991

The new signal process circuit using ISFETs as two input devices of a MOS differential amplifier stage for application to a ISFET biosensor was developed and its operational characteristics simulated. For a single chip integration of ISFETs, developed signal process circuit and metal reference electrode, serial studies including process development and chip layout was carried out.

• ETRI Journal
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• v.27 no.5
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• pp.539-544
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• 2005

An analog CMOS vision chip for edge detection with power consumption below 20mW was designed by adopting electronic switches. An electronic switch separates the edge detection circuit into two parts; one is a logarithmic compression photocircuit, the other is a signal processing circuit for edge detection. The electronic switch controls the connection between the two circuits. When the electronic switch is OFF, it can intercept the current flow through the signal processing circuit and restrict the magnitude of the current flow below several hundred nA. The estimated power consumption of the chip, with $128{\times}128$ pixels, was below 20mW. The vision chip was designed using $0.25{\mu}m$ 1-poly 5-metal standard full custom CMOS process technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.470-480
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• 2016

The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical silicon-surface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.1
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• pp.47-52
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• 2019

Micro-LEDs show lower efficiencies compared to general LEDs having large areas. Simulations were carried out using ray-tracing software to investigate the change in light extraction efficiency and light distribution according to chip-size of blue flip-chip micro-LEDs (FC ${\mu}-LEDs$). After fixing the height of the square FC ${\mu}-LED$ chip at $158{\mu}m$, the length of one side was varied, with dimensions of 2, 5, 10, 30, 50, 100, 300, and $500{\mu}m$. The highest light-extraction efficiency was obtained at $10{\mu}m$, beyond which the efficiency decreased as the chip-size increased. The chip size-dependence of the FC ${\mu}-LEDs$ both without the patterned sapphire substrate, as well as vertical FC ${\mu}-LEDs$, were analyzed.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.25-28
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• 2000

In this paper, we assume various number of multipaths in one chip duration according to spreading bandwidth. And we take into account of the effects of autocorrelation and relative phases among multipath components within one chip duration, and analyze fading effects. We derive the average error probability for different number of users. Then, we compare the performance of W-CDMA systems with different bandwidths. From the simulation results for different band-widths, wideband CDMA systems show better performance than narrowband CDMA systems in vehicular and pedestrian environments.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.165-168
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• 2000

A hardware architecture to implement the SEED block cipher algorithm into one chip is described. Each functional unit is designed with VHDL hardware description language and synthesis tools. The designed hardware receives a 128-bit block of plain text input and a 128-bit key, and generates a 128-bit cipher block after 16-round operations after 8 clocks. The encryption time is within 20 nsec.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.222-224
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• 2000

This Paper investigates the speed control of Switched reluctance motor(SRM) using one chip microcomputer The SRM has the advantages of simple structure low rotor inertia. and high efficiency. The Position sensor is essential in SRM in order to synchronize the Phase excitation to the rotor position. The proposed system consists of phase locked loop controller, switching angle controller and inverter. The Performances in the Proposed system are verified through the experiment.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.171-174
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• 2000

In stead of RF module which has been used conventionally in many remote measurement applications, a new type of remote measurement system based on PCS(Personal communication system) and one chip Microcontroller is proposed in this work. PCS has many advantages with respect to cost reliability, communication quality, and so on. The proposed system consists of three different modules: PCS module, micro-controller module, and sensor module. System configuration as well as illustrative experiments will be described in detail.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.168-170
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• 1994

Carbide-tipped twist drill of new type which is better than traditional H.S.S twist drill has been developed successfully to drill steel work-pieces with high speed. This new carbide drill consists of a characteristic flature of special shape of cutting edge, chip pocket, and flute. The special design of the chip pocket and the flute guarantees both periodic fracture and smooth transport of chips along the flute. The carbide-tipped twist drill also allows one to apply more drilling force than conventional one and produce holes with high accuracy.