Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2000.06b
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- Pages.165-168
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- 2000
Study of one chip SEED block cipher
SEED 블록 암호 알고리즘의 단일 칩 연구
Abstract
A hardware architecture to implement the SEED block cipher algorithm into one chip is described. Each functional unit is designed with VHDL hardware description language and synthesis tools. The designed hardware receives a 128-bit block of plain text input and a 128-bit key, and generates a 128-bit cipher block after 16-round operations after 8 clocks. The encryption time is within 20 nsec.
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