• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.53-56
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• 2004

This paper presents the improved burn-in method for the reliability of SRAM in MCP Semiconductor reliability is commonly improved through the burn-in process. Reliability problem is more significant in the Multi Chip Package, because of including over two devices in a package. In the SRAM-based Multi Chip Package, the failure of SRAM has a large effect on the yield and quality of the other chips - Flash Memory, DRAM, etc. So, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the current used methods. That method is effective in detecting special failure. Finally, with the composition of some kinds of methods, we could achieve the high qualify of SRAM in Multi Chip Package.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.10
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• pp.713-719
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• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

• Journal of the Korean Society for Precision Engineering
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• v.24 no.12
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• pp.95-103
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• 2007

This paper presents a liquid cooling concept for heat rejection of high power electronic devices existing in notebook computers etc. The design, fabrication, and performance of the planar ECF pump and farced-liquid cooling system are summarized. The electro-conjugate fluid (ECF) is a kind of dielectric and functional fluids, which generates jet flows (ECF-jets) by applying static electric field through a pair of rod-like electrodes. The ECF-jet directly acts on the working fluid, so the proposed planar ECF pump needs no moving part, produces no vibration and noise. The planar ECF pump, consists of a pump housing and electrode substrate, achieves maximum flow rate and output pressure of $5.5\;cm^3/s$ and 7.2 kPa, respectively, at an applied voltage of 2.0 kV. The farced-liquid cooling system, constructed with the planar ECF pump, liquid-cooled heat sink and thermal test chip, removes input power up to 80 W keeping the chip surface temperature below $70\;^{\circ}C$. The experimental results demonstrate that the feasibility of forced-liquid cooling system using ECF is confirmed as an advanced cooling solution on the next-generation high power electronic devices.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.3
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• pp.10-17
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• 2024

This paper discusses Chip On Film (COF) technology, one of the key technologies in flexible packaging to enable miniaturization and flexibility of electronic devices. COF attaches Display Driver IC (DDI) directly to a flexible polyimide substrate, enabling lightweight and reduced thickness for high-resolution displays. COF technology is primarily used in high-performance display panels, such as organic light emitting diode (OLED) displays, and plays a key role in portable electronic devices, such as smartphones and wearable devices. This study analyzes the key components of COF and advances in bonding technology. In particular, the introduction of modern bonding techniques, such as thermo-compression bonding and thermo-sonic bonding, has led to significant improvements in bonding reliability and electrical performance. These bonding techniques enhance the mechanical stability of COF packages while maintaining high electrical connectivity in fine-pitch structures. This paper will discuss the future development of COF bonding technology and its challenges and explore its potential as a next-generation display and advanced packaging technology.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.171-173
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• 2000

In this paper, we present a new interpolation method for the color filter away(CFA). In order to capture color images. typical input devices use a single chip CCD imaging sensor with color filter array. As a result, the single chip CCD does not provide sufficient color resolutions since it arranges different color filters sequentially on a single CCD, resulting in aliasing noise and loss of resolution. In order to reconstruct high quality color images, we propose to use the interpolation algorithm using high order B-splines. Experiments show promising results.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2240-2243
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• 2003

In this paper. we present a new speech recognition system using DSP chip. DSP chip used TMS320c6711 of TI. We designed hardware system including acoustic model, word list and code book in flash memory. The word candidates are recognized based on CV, VCCV, and VC units HMM. This system can be applied to various electric ＆ electronic devices: home automation, robotics etc.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.12
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• pp.1021-1026
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• 2002

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.10a
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• pp.39-45
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• 2000

A small camera module fabricated by including bare chip bonding methods is utilized to realize advanced mobile devices. One of the driving forces is the TOG (Tape On Glass) bonding method which reduces the packaging size of the image sensor clip. The TOG module is a new thinner and smaller image sensor module, using flip chip interconnection method with the ACP (Anisotropic Conductive Paste). The TOG production process was established by determining the optimum bonding conditions for both optical glass bonding and image sensor clip bonding lo the flexible PCB. The bonding conditions, including sufficient bonding margins, were studied. Another bonding method is the flip chip bonding method for DSP (Digital Signal Processor) chip. A new AC\ulcorner was developed to enable the short resin curing time of 10 sec. The bonding mechanism of the resin curing method was evaluated using FEM analysis. By using these flip chip bonding techniques, small camera module was realized.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.381-382
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• 2015

Small devices such as MLCC, sample inspection on the processing is not easy. If you can proceed with the sample inspection, the production process will be able to maximize the MLCC production efficiency. In this study, to minimize the interference of operator, and to maximize the operating efficiency of the equipment. Use image processing techniques for its extracts the position and angle of the MLCC. Implements an automatic inspection system with the high productivity.It is possible to inspect the final six MLCC devices. And once we Pick-Up to 200 Chip to check the accuracy of 98.4%. Based on the results of various studies are in progress to be expected to be applicable to the automatic inspection equipment side development of a variety of small devices.

• Journal of Biomedical Engineering Research
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• v.36 no.4
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• pp.86-94
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• 2015

In order for medical devices to be used outside hospital, they have to be not only of small size but also power consumption has to be kept at low level. This study investigates the feasibility of application of ADS1298 ECG single-chip solution developed by Texas Instruments Inc. for use in development of a new platform for diagnostic resting ECG. To prove the feasibility of commercial products based on the ADS1298 chip, the performance of the ADS1298 chip was measured in terms of input impedance, common mode rejection, frequency response, and input dynamic range using the testing method under the suitability criteria of the IEC 60601-2-25 standard. Result of the this study shows that commercialization of the ECG products based on the ADS1298 ECG single-chip solution that satisfies the international standards would be possible, if the manufactures take the filter characteristics into account in building a new platform for diagnostic resting ECG.