• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권6호
• /
• pp.832-841
• /
• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• 전자통신동향분석
• /
• 제35권2호
• /
• pp.89-103
• /
• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• 전자통신동향분석
• /
• 제35권2호
• /
• pp.120-136
• /
• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• 전자통신동향분석
• /
• 제35권2호
• /
• pp.104-119
• /
• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Molecules and Cells
• /
• 제45권2호
• /
• pp.76-83
• /
• 2022

Neurons-on-a-Chip technology has been developed to provide diverse in vitro neuro-tools to study neuritogenesis, synaptogensis, axon guidance, and network dynamics. The two core enabling technologies are soft-lithography and microelectrode array technology. Soft lithography technology made it possible to fabricate microstamps and microfluidic channel devices with a simple replica molding method in a biological laboratory and innovatively reduced the turn-around time from assay design to chip fabrication, facilitating various experimental designs. To control nerve cell behaviors at the single cell level via chemical cues, surface biofunctionalization methods and micropatterning techniques were developed. Microelectrode chip technology, which provides a functional readout by measuring the electrophysiological signals from individual neurons, has become a popular platform to investigate neural information processing in networks. Due to these key advances, it is possible to study the relationship between the network structure and functions, and they have opened a new era of neurobiology and will become standard tools in the near future.

• ETRI Journal
• /
• 제36권3호
• /
• pp.367-373
• /
• 2014

With high bandwidth, low interference, and low power consumption, optical network-on-chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path-setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non-blocking $6{\times}6$ optical router is designed to support the new method. The simulation results show the new path-setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot-I, and hotspot-II traffic patterns, respectively. The end-to-end delay performance is also improved.

• 전자공학회논문지
• /
• 제49권9호
• /
• pp.259-269
• /
• 2012

전원 전압이 낮아지고, 칩의 동작 속도가 빨라짐에 따라 온-칩 인덕턴스를 포함한 power distribution network (PDN) 분석이 중요해 질 것으로 예측된다. 본 논문에서는 일반적인 온-칩 전력 격자 구조에 적용시킬 수 있는 효과적인 인덕턴스 추출방법에 대해 제안한다. Chip layout에 적용할 수 있는 loop 인덕턴스 모델을 제시하고, 그 모델을 사용하여 post layout RC extraction netlist로 부터 인덕턴스를 포함한 netlist를 추출할 수 있는 tool을 개발하였다. 제안된 loop 인덕턴스 모델과 개발된 tool의 정확성은 회로 simulation을 통해 PEEC 모델과 비교하여 검증하였다. 인덕턴스 추출 방법을 실제 chip layout에 적용시켜 on-chip inductance를 포함한 PDN의 voltage fluctuation을 예측하였다. 패키지와 PCB 모델을 포함한 co-simulation 모델을 구성하여 on-chip inductance의 영향을 분석하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
• /
• pp.146-150
• /
• 2001

Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe. And the cascade transmission matrix conversion was performed. The same measurements and conversion techniques were conducted on the assembled test chip and substrate at the same frequency range. Then impedance values in ACF flip-chip interconnection were extracted from cascade transmission matrix. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of SiO$_2$filler to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. High frequency behavior of metal Au stud bumps was investigated. The resonance frequency of the metal stud bump interconnects is higher than that of ACF flip-chip interconnects and is not observed at the microwave frequency band. The extracted model parameters of adhesive flip chip interconnects were analyzed with the considerations of the characteristics of material and the design guideline of ACA flip chip for high frequency applications was provided.

• 대한전자공학회논문지SD
• /
• 제44권8호
• /
• pp.80-88
• /
• 2007

매우 복잡한 시스템의 보다 효율적인 설계를 위한 차세대 SoC를 위해 중요한 것은 시스템의 고적용성과 고확장성이다. 이를 위해 최근 들어 급속히 관심이 높아지는 것이 계산 모듈중심의 시스템 설계를 탈피하여 통신 중심으로 시스템 설계를 보는 communication-based 설계 방법론이며, 그 중 대표적으로 많은 관심을 모으고 있는 것이 Network-on-Chip (NoC)이다. 이는 모듈간의 직접적인 연결에 의한 데이터의 통신 구조를 가진 일반적인 SoC 설계에서의 취약한 확장성과 통신 구조의 고정성을 극복하기 위해, 데이터를 패킷화하고, 이를 네트워크 인터페이스 및 라우터에 의한 가변적인 구조에 의해 전송함으로써 통신 구조의 적용성과 확장성을 제공하려는 노력이다. 하지만 확장성과 적용성에 치중하다 보면 성능과 면적에 대한 비용이 너무 커져서 실제로 기존의 연결 방법과 비교하여 실용성이 없을 수 있다. 그래서 본 연구에서는 통신 패턴의 면밀한 분석을 통하여 매우 성능에 중요하고 또 빈번한 통신 패턴에 대해서는 기존의 연결 방식을 고수하면서, 전체적인 연결성 및 확장성을 유지하는 알고리즘을 제시한다. 이 방법을 통해서 최소 30%의 네트워크 인터페이스 및 라우터 구조가 훨씬 간단한 구조로 바뀔 수 있었으며, 이로 인한 연결성 (connectivity) 및 확장성에 대한 손실은 거의 없었다. 시뮬레이션 결과에 의하면 통신 구조의 최적화를 통해서 연결에 소요되는 시간적 성능은 49.19% 향상되었고 면적의 측면에서도 24.03% 향상되었음이 입증되었다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.869-872
• /
• 2005

In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.