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http://dx.doi.org/10.5573/JSTS.2016.16.6.832

Energy-efficient Custom Topology Generation for Link-failure-aware Network-on-chip in Voltage-frequency Island Regime  

Li, Chang-Lin (College of Information and Communication Engineering, Sungkyunkwan University)
Yoo, Jae-Chern (College of Information and Communication Engineering, Sungkyunkwan University)
Han, Tae Hee (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.16, no.6, 2016 , pp. 832-841 More about this Journal
Abstract
The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.
Keywords
Voltage-frequency island; network-on-chip; link failure; custom topology generation; energy optimization;
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