• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.27-33
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• 2011

Recently many display devices support the digital display interface as display market growth. DisplayPort is a next generation display interface at the PC, projector and high definition content applications in more widely used connection solution development. This paper implements multiple streams based on the behavior of the main link that is suitable for the display port v1.1a standard. The limit point of Displayport, interface between the Sink Device and Sink Device is also implemented. And two or more differential image data are enable to output the result through four Lanes stated in display port v1.1a, of two or more display devices without the addition of a separate Lane. The Multiple Video Streaming Controller is implemented with 6,222 ALUTs and 6,686 register, 999,424 of block memory bits synthesized using Quartus II at Altera Audio/Video Development board (Stratix II GX FPGA Chip).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.61-68
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• 2005

A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.74-84
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• 2000

This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.47-56
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• 2008

An RFID system comprises a reader and a tag, and this paper focuses on a tag design. A UHF tag is activated by energy supply using electromagnetic waves and energy reflection through impedance mismatching. The tag uses a $0.25{\mu}m$ CMOS process and comprises a digital part executing tag protocols, a 512-bit memory, and an analog part having a rectifier, a modulation/demodulation unit, a clock generator, etc. The total dimension of the tag, including a saw line, is $750{\mu}m*750{\mu}m$ and the power consumption of the tag consumption power is about $17.8{\mu}W$ at a supply voltage of 2V.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Journal of Information Processing Systems
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• v.17 no.1
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• pp.51-62
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• 2021

On-chip caches of graphics processing units (GPUs) have contributed to improved GPU performance by reducing long memory access latency. However, cache efficiency remains low despite the facts that recent GPUs have considerably mitigated the bottleneck problem of L1 data cache. Although the cache miss rate is a reasonable metric for cache efficiency, it is not necessarily proportional to GPU performance. In this study, we introduce a second key determinant to overcome the problem of predicting the performance gains from L1 data cache based on the assumption that miss rate only is not accurate. The proposed technique estimates the benefits of the cache by measuring the balance between cache efficiency and throughput. The throughput of the cache is predicted based on the warp occupancy information in the warp pool. Then, the warp occupancy is used for a second bypass phase when workloads show an ambiguous miss rate. In our proposed architecture, the L1 data cache is turned off for a long period when the warp occupancy is not high. Our two-level bypassing technique can be applied to recent GPU models and improves the performance by 6% on average compared to the architecture without bypassing. Moreover, it outperforms the conventional bottleneck-based bypassing techniques.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Smart Structures and Systems
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• v.8 no.1
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• pp.39-52
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• 2011

We are developing a biomimetic robot based on the Sea Lamprey. The robot consists of a cylindrical electronics bay propelled by an undulatory body axis. Shape memory alloy (SMA) actuators generate propagating flexion waves in five undulatory segments of a polyurethane strip. The behavior of the robot is controlled by an electronic nervous system (ENS) composed of networks of discrete-time map-based neurons and synapses that execute on a digital signal processing chip. Motor neuron action potentials gate power transistors that apply current to the SMA actuators. The ENS consists of a set of segmental central pattern generators (CPGs), modulated by layered command and coordinating neuron networks, that integrate input from exteroceptive sensors including a compass, accelerometers, inclinometers and a short baseline sonar array (SBA). The CPGs instantiate the 3-element hemi-segmental network model established from physiological studies. Anterior and posterior propagating pathways between CPGs mediate intersegmental coordination to generate flexion waves for forward and backward swimming. The command network mediates layered exteroceptive reflexes for homing, primary orientation, and impediment compensation. The SBA allows homing on a sonar beacon by indicating deviations in azimuth and inclination. Inclinometers actuate a bending segment between the hull and undulator to allow climb and dive. Accelerometers can distinguish collisions from impediment to allow compensatory reflexes. Modulatory commands mediate speed control and turning. A SBA communications interface is being developed to allow supervised reactive autonomy.