• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.855-858
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• 1998

본 연구에서는 MML(merged memory logic)구조를 갖는 스캔라인 컨버터를 설계하여 제안한다. 비월주사 방식인 TV 비디오 신호를 FIFO 메모리에 저장하여 순차주사방식인 VGA 비디오 시모호 변환하는 주사선 변환기를 MML 개념으로 설계하였다. MML 회로는 VHDL로 설계하여 V-system으로 시뮬레이션을 수행하고 altera FPGA에 구현한 후, TV 비디오 신호를 PC 모니터로 보기 위한 외장형 tV 수신 시스템에 적용하여 성능을 검증했다. MML 개념으로 설계된 컨버터는 system-on-a-chip 설계의 첫 단계로 메모리와 로직부분으로 구성된 일반적인 컨버터보다 효율적인 시스템 설계를 할 수 있다.

• IE interfaces
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• v.10 no.1
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• pp.57-65
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• 1997

Less researches on AGV(Automated Guided Vehicle) path configurations have been conducted so far while more studies have been placed in determining AGV guide path directions and pick-up/drop-off station locations, and routing/dispatching/scheduling strategies. In practice plenty of concerns fall in preventing deadlock and simplifying AGV system control through an appropriate AGV path configuration. In order to meet those requirements, a new AGV path configuration, inter-loop stocker type is introduced here. The stocker serves as relaying material between loops as well as stocking material. Automated material handling systems using AGVs play an important role in semiconductor industry including TFT LCD and memory/non-memory chip. A practical example of implementing the inter-loop stocker concept successfully in the TFT LCD fab is presented in this paper.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.317-321
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• 1989

The fully digitalized inverter has some difficulties in implementation because of the limitation of available memory capacity and computation time. In this paper schemes suitable for a one-chip microprocessor-based realization, which linearize notch angles of selected harmonic elimination (SHE) PWM, are presented. Also the detailed description of the scheme along with the realization is described. The simulation and experiment results show that proposed schemes have the predicted advantages such as good voltage waveforms and a memory-saving.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.80-90
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• 2016

Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a low-cost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.

• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.664-665
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• 2013

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.617-620
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• 2002

본 논문에서는 single bank와 multi bank FIFO를 지원하는 CMOS FIFO memory compiler를 개발 검증하였다. 이 컴파일러를 사용해서 설계자는 구현하고자 하는 어플리케이션에 적합한 high speed, high density, low power를 갖는 on-chip memory를 빠른 시간에 만들어 낼 수 있으므로 설계 시간을 절약할 수 있다. 이와 더불어 설계된 FIFO 의 시뮬레이션을 지원하기위한 Verilog 시뮬레이션 모델을 제공하였다. 현재 FIFO를 구성하는 단위 셀들은 0.6um 3-metal 공정을 이용하여 설계하였으며 공정의 변화에 따라 대상 공정에 맞도록 단지 몇 개의 단위 셀만을 재 설계하고 그에 대한 정보를 갱신해줌으로써 공정의 변화에 대처 할 수 있도록 하였다. 설계된 컴파일러를 이용해 생성된 FIFO 는 표준 셀 라이브러리를 이용한 합성 가능한 FIFO에 대하여 $16bit{\times}16word$ FIFO에서 면적면에서 93%, 속도면에서 70%의 향상을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1195-1201
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• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.

• Journal of IKEEE
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• v.24 no.2
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• pp.559-569
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• 2020

One of the deep-running algorithms, CNN's artificial intelligence application uses off-chip memory to store data on the Convolution Layer. DMA can reduce processor load at every data transfer. It can also reduce application performance degradation by varying the order in which data from the Convolution layer is transmitted to the global buffer of the accelerator. For basic layouts with continuous memory addresses, SG-DMA showed about 3.4 times performance improvement in pre-setting DMA compared to using ordinaly DMA, and for Ideal layouts with discontinuous memory addresses, the ordinal DMA was about 1396 cycles faster than SG-DMA. Experiments have shown that a combination of memory data layout and DMA can reduce the DMA preset load by about 86 percent.