• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.992-998
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• 2009

We investigated the influence of organic solvents on the droplet properties of 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS-pentacene), which was used for semiconductor of organic thin film transistors (OTFTs) and deposited by ink jet printing. From the result of the investigation, the conditions of a suitable solvent is that boiling point should be above $200^{\circ}C$ to reduce coffee stain and the surface tension above 32 dyn/cm to decrease the droplet size. Consequently, we selected tetralin which have a high boiling point ($207^{\circ}C$) and high surface tension (34.3 dyn/cm) as the solvent for TIPS-pentacene, and applied it to OTFTs. In fabrication process the conventional bank process employing photolithography and etching process was replaced by ink jet printed bank process, resulting in simplifying the process. Especially, polyvinylphenol was used for the bank, and the high hydrophobicity could improve the confinement of TIPS molecules inside the bank, enhancing the performance over the conventional hydrophilic polyvinylalcohol bank. The mobility was $0.18\;cm^2/Vs$, current on/off ratio $2.09{\times}10^5$, subthreshold slope 0.42 V/dec, and off state current $0.049\;pA/{\mu}m$.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.291.1-291.1
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• 2016

Graphene by one of the two-dimensional (2D) materials has been focused on electronic applications due to its ultrahigh carrier mobility, outstanding thermal conductivity and superior optical properties. Although graphene has many remarkable properties, graphene devices have low on/off current ratio due to its zero bandgap. Despite considerable efforts to open its bandgap, it's hard to obtain appropriate improvements. To solve this problem, heterojunction barristor was proposed based on graphene. Mostly, this heterojunction barristor is made by transition metal dichalcogenides (TMDs), such as molybdenum disulfide ($MoS_2$) and tungsten diselenide ($WSe_2$), which have extremely thickness scalability of TMDs. The heterojunction barristor has the advantage of controlling graphene's Fermi level by applying gate bias, resulting in barrier height modulation between graphene interface and semiconductor. However, charged impurities between graphene and $SiO_2$ cause unexpected p-type doping of graphene. The graphene's Fermi level modulation is expected to be reduced due to this p-doping effect. Charged impurities make carrier mobility in graphene reduced and modulation of graphene's Fermi level limited. In this paper, we investigated theoretically and experimentally a relevance between graphene's Fermi level and p-type doping. Theoretically, when Fermi level is placed at the Dirac point, larger graphene's Fermi level modulation was calculated between -20 V and +20 V of $V_{GS}$. On the contrary, graphene's Fermi level modulation was 0.11 eV when Fermi level is far away from the Dirac point in the same range. Then, we produced two types heterojunction barristors which made by p-type doped graphene and graphene treated 2.4% APTES, respectively. On/off current ratio (32-fold) of graphene treated 2.4% APTES was improved in comparison with p-type doped graphene.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.292-294
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• 2016

이황화몰리브덴을 활용한 전계효과트랜지스터(Field Effect Transistor)는 채널 물질의 우수한 특성으로 차세대 저전력 고성능 스위치와 광전소자로 주목받고있다. Underlap 게이트 구조에서 게이트 길이(L_G), 절연체 두께(T), 절연체 상대유전율(${\varepsilon}_r$)에 따라 변화하는 소자특성을 분석하여 저전력 고성능 $MoS_2$ 전계효과트랜지스터를 위한 게이트 구조 최적화방법을 모색하였다. EDISON simulator 중 Tight-binding NEGF 기반 TMD FET 소자 성능 및 특성 해석용 S/W를 활용하여 게이트 구조에 따른 게이트 전압 - 드레인 전류 상관관계(transfer characteristic)를 얻고, Y-function method를 이용하여 채널 유효전하이동도(Effective Mobility), Sub-threshold Swing, on/off 전류비(on/off current ratio)를 추출하여 비교 분석하였다. 시뮬레이션으로 추출한 소자의 최대 채널 유효전하이동도는 $37cm^2V^{-1}s^{-1}$, on/off 전류비는 $10^4{\sim}10^5$, Sub-threshold Swing은 ~38mV/dec 수준을 보였다.

• Journal of Industrial and Engineering Chemistry
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• v.68
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• pp.399-405
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• 2018

We report the fabrication of organic field-effect transistors (OFETs) via spray coating of electrochemically exfoliated graphene (EEG) and conducting polymer hybrid as electrodes. To reduce the roughness and sheet resistance of the EEG electrodes, subsequent coating of conducting polymer (poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS)) and acid treatment was performed. After that, active channel layer was developed by spin coating of semiconducting poly(3-hexylthiophene) on the hybrid electrodes to define the bottom gate bottom contact configuration. The OFET devices with the EEG/PEDOT:PSS hybrid electrodes showed a reasonable electrical performances (field effect mobility = $0.15cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^2$, and threshold voltage = -1.57V). Furthermore, the flexible OFET devices based on the Polydimethlsiloxane (PDMS) substrate and ion gel dielectric layer exhibited higher electrical performances (field effect mobility = $6.32cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^3$, and threshold voltage = -1.06V) and excellent electrical stability until 1000 cycles of bending test, which means that the hybrid electrode is applicable to various organic electronic devices, such as flexible OFETs, supercapacitors, organic sensors, and actuators.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• Journal of Power Electronics
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• v.19 no.4
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• pp.846-857
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• 2019

Voltage step-down converters are very popular in distributed power systems, voltage regular modules, electric vehicles, etc. However, a high step-down voltage ratio is required in many applications to prevent the traditional buck converter from operating at extreme duty cycles. In this paper, a series capacitor interleaved buck converter with a soft switching technique is proposed. The DC voltage ratio of the proposed converter is half that of the traditional buck converter and the voltage stress across the one main switch and the diodes is reduced. Moreover, by paralleling the series connected auxiliary switch and the auxiliary inductor with the main inductor, zero voltage transition (ZVT) of the main switches can be obtained without increasing the voltage or current stress of the main power switches. In addition, zero current turned-on and zero current switching (ZCS) of the auxiliary switches can be achieved. Furthermore, owing to the presence of the auxiliary inductor, the turned-off rate of the output diodes can be limited and the reverse-recovery switching losses of the diodes can be reduced. Thus, the efficiency of the proposed converter can be improved. The DC voltage gain ratio, soft switching conditions and a design guideline for the critical parameters are given in this paper. A loss analysis of the proposed converter is shown to demonstrate its advantages over traditional converter topologies. Finally, experimental results obtained from a 100V/10V prototype are presented to verify the analysis of the proposed converter.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.293.2-293.2
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• 2016

The In this paper, we have fabricated the solution processed In-Ga-ZnO thin film transistors (IGZO TFTs) by varying indium and gallium ratio. The indium ratio of IGZO TFTs was changed from 1 to 5 at fixed gallium and zinc oxide atomic percent of 1:1 and gallium ratio was varied from 1 to 5 at fixed indium and zinc oxide atomic percent of 1:1. When the indium ratio was increased at fixed gallium and zinc oxide ratio of 1:1, threshold voltage was negatively shifted from 1.03 to -6.18 V and also mobility was increased from 0.018 to $0.076cm2/V{\cdot}sec$. It means that the number of carriers in IGZO TFTs were increased due to great formation of the oxygen vacancies which generate electrons. In contrast, when the gallium ratio was increased in IGZO TFTs with indium and zinc oxide ration of 1:1, the on/off current ratio was increased from $1.88{\times}104$ to $2.22{\times}105$. It is because gallium have stronger chemical bonds with oxygen than that with the zinc and indium ions that lead to the decreased in electron concentration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.3
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• pp.147-151
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• 2016

Graphene has a monolayer crystal structure formed with C-atoms and has been used as a base layer of HETs (hot electron transistors). Graphene HETs have exhibited the operation at THz frequencies and higher current on/off ratio than that of Graphene FETs. In this article, we report on the preliminary results of current characteristics from the HETs which are fabricated utilizing highly doped Si collector, graphene base, and 5 nm thin $Al_2O_3$ tunnel layers between the base and Ti emitter. We have observed E-B forward currents are inherited to tunneling through $Al_2O_3$ layers, but have not noticed the Schottky barrier blocking effect on B-C forward current at the base/collector interface. At the common-emitter configuration, under a constant $V_{BE}$ between 0~1.2V, $I_C$ has increased linearly with $V_{CE}$ for $V_{CE}$ < $V_{BE}$ indicating the saturation region. As the $V_{CE}$ increases further, a plateau of $I_C$ vs. $V_{CE}$ has appeared slightly at $V_{CE}{\simeq}V_{BE}$, denoting forward-active region. With further increase of $V_{CE}$, $I_C$ has kept increasing probably due to tunneling through thin Schottky barrier between B/C. Thus the current on/off ration has exhibited to be 50. To improve hot electron effects, we propose the usage of low doped Si substrate, insertion of barrier layer between B/C, or substrates with low electron affinity.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.28-31
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• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.