• Proceedings of the Materials Research Society of Korea Conference
• /
• 2010.05a
• /
• pp.31.1-31.1
• /
• 2010

Various ZnO nanostructures were synthesized and ZnO nanostructure-based self-assembled transistors were fabricated. Compared to spindle and flower like nanostructure, the ZnO nanorod (NR) structure showed much stronger gate controllability, and greatly enhanced device performance, demonstrating that this structural variation leads to significant differences of the nanostructure network-based device performance. Also, patterned dry transfer-printing technique that can generate monolayer-like percolating networks of ZnO NRs has been developed. The method exploits the contact area difference between NR-NR and NR-substrate, rather than elaborate tailoring of surface chemistry or energetic. The devices prepared by the transferring method exhibited on/off current ratio, and mobility of ${\sim}2.7{\times}10^4$ and ${\sim}1.03\;cm^2/V{\cdot}s$, respectively. Also, they exhibited showing lower off-current and stronger gate controllability due to defined-channel between electrodes and monolayer-like network channel configuration. With multilayer stacks of nanostructures on stamp, the monolayer-like printing can be repeated many times, possibly on large area substrate, due to self-regulating printing characteristics. The method may enable high-performance macroelectronics with materials that have high aspect ratio.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2000.01a
• /
• pp.69-70
• /
• 2000

There are currently considerable interest in the applications of conjugated polymers, oligomers, and small molecules for thin-film electronic devices. Organic materials have potential advantages to be utilized as semiconductors in field-effect transistors and light-emitting diodes. In this study, pentacene thin-film transistors (TFTs) were fabricated on glass substrate. Aluminums were used for gate electrodes. Silicon dioxide was deposited as a gate insulator by PECVD and patterned by reactive ion etching (R.I.E). Gold was used for the electrodes of source and drain. The active semiconductor pentacene layer was thermally evaporated in vacuum at a pressure of about $10^{-8}$ Torr and a deposition rate $0.3{\AA}/s$. The fabricated devices exhibited the field-effect mobility as large as 0.07 $cm^2/V.s$ and on/off current ratio as larger than $10^7$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.440-440
• /
• 2011

We report on the non-volatile memory characteristics of a bistable organic memory (BOM) device with Au nanoparticles (NPs) embedded in a conducting poly N-vinylcarbazole (PVK) colloids hybrid layer deposited on flexible polyethylene terephthalate (PET) substrates. Transmission electron microscopy (TEM) images show the Au nanoparticles distributed isotropically around the surface of a PVK colloid. The average induced charge on Au nanoparticles, estimated using the C-V hysteresis curve, was large, as much as 5 holes/NP at a sweeping voltage of ${\pm}3$ V. The maximum ON/OFF ratio of the current bistability in the BOM devices was as large as $1{\times}105$. The cycling endurance tests of the ON/OFF switching exhibited a high endurance of above $1.5{\times}105$ cycles and a high ON/OFF ratio of ~105 could be achieved consistently even after quite a long retention time of more than $1{\times}106$ s.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.10
• /
• pp.2305-2309
• /
• 2010

In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off and drain induced barrier lowing have been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.765-767
• /
• 2010

In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off has been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.29 no.2
• /
• pp.69-74
• /
• 2016

In this study, we proposed an a-IGZO (amorphous In-Ga-Zn-O) TFT (thin-film transistor) with off-planed source/drain structure. Furthermore, two different electrode materials (ITO and Ti) were applied to the source and drain contacts for performance improvement of a-IGZO TFTs. When the ITO with a large work-function and the Ti with a small work-function are applied to drain electrode and source contact, respectively, the electrical performances of a-IGZO TFTs were improved; an increased driving current, a decreased leakage current, a high on-off current ratio, and a reduced subthreshold swing. As a result of gate bias stress test at various temperatures, the off-planed S/D a-IGZO TFTs showed a degradation mechanism due to electron trapping and both devices with ITO-drain or Ti-drain electrode revealed an equivalent instability.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.384-384
• /
• 2012

We report nonvolatile memory properties of poly (3, 4-ethylenedioxythiophene) (PEDOT) thin films grown by vapor phase polymerization using FeCl3 as an oxidant. Liquid-bridge-mediated transfer method was employed to remove FeCl3 for generation of pure PEDOT thin films. From the electrical measurement of memory device, we observed voltage induced bipolar resistive switching behavior with ON/OFF ratio of 103 and reproducibility of more than 103 dc sweeping cycles. ON and OFF states were stable up to 104 seconds without significant degradation. Cyclic voltammetry data illustrates resistive switching effect can be attributed to formation and rupture of conducting paths due to oxidation and reduction of PEDOT. The maximum current before reset process was found to be increase linearly with increase in compliance current applied during set process.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.111-114
• /
• 2000

Single Electron Transistor Logic (SETL) can be characterized by HSPICE simulation using a SPICE macro model. First, One unit SET is characterized by Monte-carlo simulation and then we fit SPICE macro-modeling equations to its characteristics. Second, using this unit SET, we simulate the transient characteristics of two-input NAND gate in both the static and dynamic logic schemes. The dynamic logic scheme shows more stable operation in terms of logic-swing and on/off current ratio. Also, there is a merit that we can use the SET only as current on-off switch without considering the voltage gain.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1336_1337
• /
• 2009

본 논문에서는 유기 박막 트랜지스터의 전극을 잉크젯 프린팅과 스크린 프린팅 방법을 이용하여 유기 박막 트랜지스터를 제작하였다. 전극으로 PEDOT:PSS와 Ag 잉크를 사용하였고, 게이트 절연막으로 polymethyl methacrylate (PMMA)와 poly(4-vinylphenol) (PVP)를 사용하였다. 유기물 활성층으로 pentacene을 진공 증착하였다. 잉크젯 프린팅 방법을 이용하여 제작한 유기 박막 트랜지스터는 전계이동도 (${\mu}_{FET}$) $0.068\;cm^2$/Vs, 문턱전압 ($V_{th}$) -15 V, 전류 점멸비 ($I_{on}/I_{off}$ current ratio) >$10^4$의 전기적 특성을 보였고, 스크린 인쇄 방법을 이용하여 제작한 유기 박막 트랜지스터는 전계이동도 (${\mu}_{FET}$) $0.016\;cm^2$/Vs, 문턱전압 ($V_{th}$) 6 V, 전류 점멸비 ($I_{on}/I_{off}$ current ratio) >$10^4$의 전기적 특성을 보였다. 이를 통하여 프린팅 방법을 이용한 유기 박막 트랜지스터 단일 소자 및 유기 전자 회로 제작의 가능성을 확인 하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.24 no.5
• /
• pp.359-363
• /
• 2011

To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.