• 대한임베디드공학회논문지
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• 제11권4호
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• pp.201-208
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• 2016

Non-volatile counter is a counter that maintains the value without external power supply. It has been used for the applications related to warranty issues to count and record certain events such as power cycles, operating time, hard resets, and timeouts. It has been conventionally implemented with volatile memory-based counter and battery backup or non-volatile memory such as EEPROM. Both of them have a lifetime issue due to the limited lifetime of the battery and the endurance of the non-volatile memory cells, which incurs significant redundancy in design. In this paper, we introduce a hybrid architecture of volatile (SRAM) and non-volatile memory (EEPROM) cells to achieve required lifetime of the non-volatile counter with smaller cost. We conduct a design space exploration of the proposed hybrid architecture with the parameters of various kinds of non-volatile memories. The analysis result shows that the proposed hybrid non-volatile counter can extend the lifetime up to 6 times compared to the battery-backup volatile memory-based implementation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.241-241
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• 2010

New non-volatile memory with high density and high work-function metal nano-dots, MND (Metal Nano-Dot) memory, was proposed and fundamental characteristics of MND capacitor were evaluated. In this work, nano-dot layer of FePt with high density and high work-function (~5.2eV) was fabricated as a charge storage site in non-volatile memory, and its electrical characteristics were evaluated for the possibility of non-volatile memory in view of cell operation by Fowler-Nordheim (FN)-tunneling. Here, nano-dot FePt layer was controlled as a uniform single layer with dot size of under ~ 2nm and dot density of ${\sim}\;1.2{\times}10^{13}/cm^2$. Electrical measurements of MOS structure with FePt nano-dot layer shows threshold voltage window of ~ 6V using FN programming and erasing, which is satisfied with operation of the non-volatile memory. Furthermore, this structure provides better data retention characteristics compared to other metal dot materials with the similar dot density in our experiments. From these results, it is expected that this non-volatile memory using FePt nano-dot layer with high dot density and high work-function can be one of candidate structures for the future non-volatile memory.

• 대한임베디드공학회논문지
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• 제8권5호
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• pp.235-242
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• 2013

Recently, the number of automotive electrical and electronic system has been increased because the requirements for the convenience and safety of the drivers and passengers are raised. In most cases, the data for controlling the various sensors and automotive electrical and electronic system used in runtime should be stored on the internal or external non-volatile memory of the ECU(Electronic Control Units). However, the non-volatile memory has a constraint with write limitation due to the hardware characteristics. The limitation causes fatal accidents or unexpected results if the non-volatile memory is not managed. In this paper, we propose a management scheme for using non-volatile memory to prolong the writing times based on AUTOSAR(AUTOmotive Open System Architecture) platform. Our proposal is implemented on the CDD(Complex Device Driver) and uses an algorithm which swaps a frequently modified block for a least modified block. Through the development of the prototype, the proposed scheme extends the lifetime of non-volatile memory about 1.08 to 2.48 times than simply using the AUTOSAR standard.

• 반도체디스플레이기술학회지
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• 제21권1호
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• pp.85-90
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• 2022

In this paper, an asynchronous nonvolatile memory module using a self-diagnosis function was designed. For the system to work, a lot of data must be input/output, and memory that can be stored is required. The volatile memory is fast, but data is erased without power, and the nonvolatile memory is slow, but data can be stored semi-permanently without power. The non-volatile static random-access memory is designed to solve these memory problems. However, the non-volatile static random-access memory is weak external noise or electrical shock, data can be some error. To solve these data errors, self-diagnosis algorithms were applied to non-volatile static random-access memory using error correction code, cyclic redundancy check 32 and data check sum to increase the reliability and accuracy of data retention. In addition, the possibility of application to an asynchronous non-volatile storage system requiring reliability was suggested.

• 대한임베디드공학회논문지
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• 제13권5호
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• pp.245-252
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• 2018

Non-volatile RAM devices have been increasingly viewed as an alternative of DRAM main memory system. However some technologies including phase-change memory (PCM) are still suffering from relatively poor write performance as well as limited endurance. In this paper, we introduce a proactive last-level cache management to efficiently hide a low write performance of non-volatile main memory systems. The proposed method significantly reduces the cache miss penalty by proactively evicting the part of cachelines when the non-volatile main memory system is in idle state. Our trace-driven simulation demonstrates 24% performance enhancement, compared with a conventional LRU cache management, on the average.

• 정보과학회 논문지
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• 제43권2호
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• pp.152-162
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• 2016

비 휘발성 메모리를 할당받아 사용하기 위해서는 비 휘발성 메모리 전용의 가비지 수집 기법이 필수적이다. 본 논문에서는 이를 위해 비 휘발성 메모리 할당 정보 관리용 메타데이터를 설계하였고 이를 Allocation Tree라고 명명하였다. 이 메타데이터는 검색 속도의 향상을 위해 트리 자료구조를 이용하여 구성되었고, 하나의 노드 안에는 할당 메모리 시작 주소와 저장소 ID 정보가 키-밸류 형태로 저장된다. 비 휘발성 메모리 공간이 부족하여 가용 공간이 70% 이하로 떨어지면 가비지 수집기가 작동되어 가비지 수집을 수행하게 되고 Allocation Tree와 사용자 데이터를 비교하여 가비지를 판정한다. 본 연구에서는 이 알고리즘을 Persistent Heap기반의 메모리 할당 플랫폼인 'HEAPO'에서 구현하여 정상적으로 동작함을 증명하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.1-10
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• 2008

The present status of technical development of a highly scalable, high-speed non-volatile PCM is overviewed. Major technical challenges are described along with solutions that are being pursued in terms of innovative device structures and fabrication technologies, new phase change materials, and new memory schemes.

• 반도체디스플레이기술학회지
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• 제14권2호
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• 한국컴퓨터정보학회논문지
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• 제23권4호
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• pp.1-8
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• 2018

In this paper, we propose an adaptive partition cache replacement policy and evaluate the performance of our scheme using various monitoring ratios to help lifetime extension of non-volatile main memory systems without performance degradation. The proposal combines conventional LRU (Least Recently Used) replacement policy and Early Eviction Zone (E2Z), which considers a dirty bit as well as LRU bits to select a candidate block. In particular, this paper shows the performance of non-volatile memory using various monitoring ratios and determines optimized monitoring ratio and partition size of E2Z for reducing the number of writebacks using cache hit counter logic and hit predictor. In the experiment evaluation, we showed that 1:128 combination provided the best results of writebacks and runtime, in terms of performance and complexity trade-off relation, and our proposal yielded up to 42% reduction of writebacks, compared with others.

• 대한임베디드공학회논문지
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• 제12권3호
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• pp.177-184
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• 2017

High performance non-volatile memory system can mitigate the gap between main memory and storage. However, no single memory devices fulfill the requirements. Non-volatile Dual In-line Memory Module (NVDIMM) consisted of DRAMs and NAND Flashes has been proposed to achieve the performance and non-volatility simultaneously. When power outage occurs, data in DRAM is backed up into NAND Flash using a small-size external energy storage such as a supercapacitor. Backup and restore operations of NVDIMM do not cooperate with the operating system in the NVDIMM standard, thus there is room to optimize its operation. This paper analysis the operation of NVDIMM and proposes a method to reduce backup and restore time. Particularly, data compression is introduced to reduce the amount of data that to be backed up and restored. The simulation results show that the proposed method reduces up to 72.6% of backup and restore time.