• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.1-9
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• 2011

Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.6
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• pp.422-426
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• 2007

Personal mobile devices equipped with non-volatile storage such as MP3 player, PMP, cellular phone, and USB memory require safety for the stored data on the devices. One of the safety requirements is secure deletion, which is removing stored data completely so that the data can not be restored illegally. In this paper, we study how to design the secure deletion on Flash memory, commonly used as storage media for mobile devices. We consider two possible secure deletion policy, named zero-overwrite and garbage-collection respectively, and analyze how each policy affects the performance of Flash memory file systems. Then, we propose an adaptive file deletion scheme that exploits the merits of the two possible policies. Specifically, the proposed scheme applies the zero-overwrite policy for small files, whereas it employs the garbage-collection policy for large files. Real implementation experiments show that the scheme is not only secure but also efficient.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.396-396
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• 2013

The resistive random access memory (ReRAM) has several advantages to apply next generation non-volatile memory device, because of fast switching time, long retentions, and large memory windows. The high mobility of monolayered graphene showed several possibilities for scale down and electrical property enhancement of memory device. In this study, the monolayered graphene grown by chemical vapor deposition was transferred to $SiO_2$ (100 nm)/Si substrate and glass by using PMMA coating method. For formation of metal-oxide nanoparticles, we used a chemical reaction between metal films and polyamic acid layer. The 50-nm thick BPDA-PDA polyamic acid layer was coated on the graphene layer. Through soft baking at $125^{\circ}C$ or 30 min, solvent in polyimide layer was removed. Then, 5-nm-thick indium layer was deposited by using thermal evaporator at room temperature. And then, the second polyimide layer was coated on the indium thin film. After remove solvent and open bottom graphene layer, the samples were annealed at $400^{\circ}C$ or 1 hr by using furnace in $N_2$ ambient. The average diameter and density of nanoparticle were depending on annealing temperature and times. During annealing process, the metal and oxygen ions combined to create $In_2O_3$ nanoparticle in the polyimide layer. The electrical properties of $In_2O_3$ nanoparticle ReRAM such as current-voltage curve, operation speed and retention discussed for applictions of transparent and flexible hybrid ReRAM device.

• Journal of the Korea Society of Computer and Information
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• v.15 no.8
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• pp.23-30
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• 2010

Flash memory is non-volatile and can retain data even after system is powered off. Besides, it has many other features such as fast access speed, low power consumption, attractive shock resistance, small size, and light-weight. As its price decreases and capacity increases, the flash memory is expected to be widely used in consumer electronics, embedded systems, and mobile devices. Flash storage systems generally adopt a software layer, called FTL. In this research, we proposed a new FTL mechanism for overcoming the major drawback of conventional block mapping algorithm. In addition to the block mapping table, a index block mapping table with a small size is used to indicate sector location. The proposed indexed block mapping algorithm by adding a small size. By the simulation result, the proposed FTL provides an enhanced speed than a conventional hybrid mapping algorithm by around 45% in average, and the requirement of mapping memory is also reduced by around 12%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.65-70
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• 2022

As fast storage has become popular, the memory management system designed for hard disks needs to be reconsidered. In this paper, we observe that memory access latency is sensitive to the page size when fast storage is adopted. We find the reason from the TLB miss rate, which has the increased impact on the memory access latency in comparison with the page fault rate, and there is trade-off between the TLB miss rate and the page fault rate as the page size is varied. To handle such situations, we model the page fault rate and the TLB miss rate accurately as a function of the page size. Specifically, we show that the power fit and the exponential fit with two terms are appropriate for fitting the TLB miss rate and the page fault rate, respectively. We validate the effectiveness of our model by comparing the estimated values from the model and real values.

• Journal of Internet of Things and Convergence
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• v.10 no.3
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• pp.19-24
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• 2024

Recent advances in large-scale data processing technologies such as big data, cloud computing, and artificial intelligence have increased the demand for high-performance storage devices in data centers and enterprise environments. In particular, the fast data response speed of storage devices is a key factor that determines the overall system performance. Solid state drives (SSDs) based on the Non-Volatile Memory Express (NVMe) interface are gaining traction, but new bottlenecks are emerging in the process of handling large data input and output requests from multiple hosts simultaneously. SSDs typically process host requests by sequentially stacking them in an internal queue. When long transfer length requests are processed first, shorter requests wait longer, increasing the average response time. To solve this problem, data transfer timeout and data partitioning methods have been proposed, but they do not provide a fundamental solution. In this paper, we propose a dual queue based scheduling scheme (DQBS), which manages the data transfer order based on the request order in one queue and the transfer length in the other queue. Then, the request time and transmission length are comprehensively considered to determine the efficient data transmission order. This enables the balanced processing of long and short requests, thus reducing the overall average response time. The simulation results show that the proposed method outperforms the existing sequential processing method. This study presents a scheduling technique that maximizes data transfer efficiency in a high-performance SSD environment, which is expected to contribute to the development of next-generation high-performance storage systems

• Korean Journal of Materials Research
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• v.20 no.5
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• pp.257-261
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• 2010

A non-volatile resistive random access memory (RRAM) device with a Cr-doped $SrZrO_3/SrRuO_3$ bottom electrode heterostructure was fabricated on $SrTiO_3$ substrates using pulsed laser deposition. During the deposition process, the substrate temperature was $650^{\circ}C$ and the variable ambient oxygen pressure had a range of 50-250 mTorr. The sensitive dependences of the film structure on the processing oxygen pressure are important in controlling the bistable resistive switching of the Cr-doped $SrZrO_3$ film. Therefore, oxygen pressure plays a crucial role in determining electrical properties and film growth characteristics such as various microstructural defects and crystallization. Inside, the microstructure and crystallinity of the Cr-doped $SrZrO_3$ film by oxygen pressure were strong effects on the set, reset switching voltage of the Cr-doped $SrZrO_3$. The bistable switching is related to the defects and controls their number and structure. Therefore, the relation of defects generated and resistive switching behavior by oxygen pressure change will be discussed. We found that deposition conditions and ambient oxygen pressure highly affect the switching behavior. It is suggested that the interface between the top electrode and Cr-doped $SrZrO_3$ perovskite plays an important role in the resistive switching behavior. From I-V characteristics, a typical ON state resistance of $100-200\;{\Omega}$ and a typical OFF state resistance of $1-2\;k{\Omega}$, were observed. These transition metal-doped perovskite thin films can be used for memory device applications due to their high ON/OFF ratio, simple device structure, and non-volatility.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1283-1288
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• 2004

Metal-ferroelectric-insulator-semiconductor(WFIS) capacitors using rapid thermal annealed LiNbO$_3$/AlN/Si(100) structure were fabricated and demonstrated nonvolatile memory operations. The capacitors on highly doped Si wafer showed hysteresis behavior like a butterfly shape due to the ferroelectric nature of the LiNbO$_3$ films. The typical dielectric constant value of LiNbO$_3$ film in the MFIS device was about 27, The gate leakage current density of the MFIS capacitor was 10$^{-9}$ A/cm$^2$ order at the electric field of 500 kV/cm. The typical measured remnant polarization(2P$_{r}$) and coercive filed(Ec) values were about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively The ferroelectric capacitors showed no polarization degradation up to 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulses of 1 MHz. The switching charges degraded only by 10 % of their initial values after 4 days at room temperature.e.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.80-84
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• 2008

We systematically investigated the resistive switching properties of thin $TiO_2$ films on Pt/Ti/$SiO_2$/Si substrates that were embedded with a Co ultra thin layer. An in-situ sputtering technique was used to grow both films without breaking the chamber vacuum. A stable bipolar switching in the current-voltage curve was clearly observed in $TiO_2$ films with an embedded Co ultra thin layer, addressing the high and low resistive state under a bias voltage sweep. We propose that the underlying origin involved in the bipolar switching may be attributed to the interface redox reaction between the Co and $TiO_2$ layers. The improved reproducible switching properties of our novel structures under forward and reverse bias stresses demonstrated the possibility of future non-volatile memory elements in a simple capacitive-like structure.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1562-1564
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• 2003

In this study, PZT thin films were fabricated using sol-gel processing onto Si/$SiO_2$/Ti/Pt substrates. PZT sol with different Zr/Ti ratio(20/80, 30/70, 40/60, 52/48) were prepared, respectively. The films were fabricated by using the spin-coating method on substrates. The films were heat treated at $450^{\circ}C,\;650^{\circ}C$ by rapid thermal annealing(RTA). The preferred orientation of the PZT thin films were observed by X-ray diffraction(XRD), and Scanning electron microscopy(SEM). All of the resulting PZT thin films were crystallized with perovskite phase. The fine crystallinity of the films were fabricated. Also, we found that the ferroelectric properties from the dielectric constant of the PZT thin films were over 600 degrees, P-E hysteresis constant. And the leakage current densities of films were lower than $10^{-8}A/cm^2$. It is concluded that the PZT thin films by sol-gel process to be convinced of application for ferroelectric memory device.