• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.25-32
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• 2011

NoC is actively being studied recently in order to overcome the limitations of shared-bus architecture. We proposed an NoC architecture which employs a buffer that plays a similar role of a proxy server in a computer network to enhance the communication efficiency of NoC architecture. In the proposed NoC architecture, whenever the master has a difficulty in communicating with the slave directly, the master communicates with the proxy server which is able to communicate with the slave on behalf of the master. With the proposed scheme in NoC, we can increase the speed and the bandwidth of communication channel. The experimental results showed that overall communication efficiency was significantly improved by sending the packets to the proxy server rather than holding them in the switch buffer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.56-65
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• 2009

As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.361-370
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• 2008

NoC is adopted for data communication between processors and IPs in MPSoC system. NoC has an advantage of scalability in that system can be easily expanded just by adding switches. However, as the number of switches increases, chip area increases as well as data transfer latency. This paper proposes an architecture that can reduce the number of switches in the system by sharing network interfaces. To reduce NI area, the modules sharing network interface use a common buffer in network interface. Experimental results show that the chip area has been reduced by 46.5% and data transfer latency by 17.1%, respectively, compared to conventional architecture.

• ETRI Journal
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• v.31 no.2
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• Journal of KIISE
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• v.43 no.2
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• pp.163-176
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• 2016

The contention overhead on the same channel in an NoC architecture can significantly increase a communication delay due to the simultaneous communication requests that occur. To reduce the overall overhead, we propose task-to-tile binding techniques for an NoC-based manycore platform, whereby it is assumed that the task mapping decision has already made. Since the NoC architecture may have multiple memory tiles as its size grows, memory clustering is used to balance the load of memory by making applications access different memory tiles. We assume that the information on the communication overhead of each application is known since it is specified in a dataflow task graph. Using this information, this paper proposes two heurisitics that perform binding of multiple tasks at once based on a proper memory clustering method. Experiments with an NoC simulator prove that the proposed heurisitic shows performance gains that are 25% greater than that of the previous binding heuristic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.359-366
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• 2016

Today's multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.26-32
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• 2008

The conventional shared bus architecture is capable of processing only one data transaction in same time. In this paper, we propose the NAWM (No Arbitration Wild Master) bus architecture that is capable of processing several data transactions in same time. After designing the master and the slave wrappers of NAWM bus architecture about AMBA system, we confirm that most of IPs of AMBA system can be a lied without modification and the added timing delay can be neglected. from simulation we deduce that more than 50% parallel processing is possible when several masters initiate slaves in NAWM bus architecture.

• Horticultural Science & Technology
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• v.33 no.3
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• pp.356-363
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• 2015

This study examined the effects of different day/night temperature regimes or silver ion on growth and flowering of passion fruit 'Tai-nung No.1'. Low temperature treatment ($20/15^{\circ}C$) caused passion fruit cultivar 'Tai-nung No.1' to fail to flower. Flowering induction occurred within a temperature range of $20-30^{\circ}C$, with no significant difference in the days to first flower bud and the total number of flower buds between plants grown at $30/25^{\circ}C$ and $25/20^{\circ}C$. However, plants grown at $30/25^{\circ}C$ exhibited their first flower buds set on the higher nodes and had higher abortion rates of flower buds than those at $25/20^{\circ}C$. Plants grown at $30/25^{\circ}C$ had the most rapid growth and the shortest plastochron. We also evaluated the effect of the ethylene response inhibitors silver nitrate ($AgNO_3$) and silver thiosulfate (STS) on growth and flowering of potted passion fruit 'Tai-nung No.1', when they were exposed to low temperature conditions ($20/15^{\circ}C$) following chemical treatments ($AgNO_3$ or STS, at 0.5 or 1.0 mM). $AgNO_3$ and STS treatments induced flower formation and initial flower bud formation within approximately two weeks at $20/15^{\circ}C$ whereas non-treated control plants exhibited no flower formation. ACC content and activity of ACC oxidase in the leaves of passion fruit 'Tai-nung No.1'exposed to low temperature conditions ($20/15^{\circ}C$) were significantly inhibited by the ethylene inhibitor treatments. These results indicate that ethylene, which is produced under low temperature conditions, plays an important role in inhibiting flower formation in passion fruit.