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NAWM Bus Architecture of High Performance for SoC  

Lee, Kook-Pyo (Dept. of Electronics Engineering, Inha University)
Yoon, Yung-Sup (Dept. of Electronics Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.9, 2008 , pp. 26-32 More about this Journal
Abstract
The conventional shared bus architecture is capable of processing only one data transaction in same time. In this paper, we propose the NAWM (No Arbitration Wild Master) bus architecture that is capable of processing several data transactions in same time. After designing the master and the slave wrappers of NAWM bus architecture about AMBA system, we confirm that most of IPs of AMBA system can be a lied without modification and the added timing delay can be neglected. from simulation we deduce that more than 50% parallel processing is possible when several masters initiate slaves in NAWM bus architecture.
Keywords
bus architecture; architecture performance; SoC; AMBA;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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