ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Mapping and Scheduling for Circuit-Switched Network-on-Chip Architecture

  • Wu, Chia-Ming (Department of Computer Science and Information Engineering, National Dong Hwa University) ;
  • Chi, Hsin-Chou (Department of Computer Science and Information Engineering, National Dong Hwa University) ;
  • Chang, Ruay-Shiung (Department of Computer Science and Information Engineering, National Dong Hwa University)
  • Received : 2008.10.17
  • Accepted : 2008.12.22
  • Published : 2009.04.30
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Abstract

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

Keywords

References

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