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An Area Efficient Network Interface Architecture  

Lee, Ser-Hoon (서강대학교 전자공학과 CAD & ES. 연구실)
Hwang, Sun-Young (서강대학교 전자공학과 CAD & ES. 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.33, no.5C, 2008 , pp. 361-370 More about this Journal
Abstract
NoC is adopted for data communication between processors and IPs in MPSoC system. NoC has an advantage of scalability in that system can be easily expanded just by adding switches. However, as the number of switches increases, chip area increases as well as data transfer latency. This paper proposes an architecture that can reduce the number of switches in the system by sharing network interfaces. To reduce NI area, the modules sharing network interface use a common buffer in network interface. Experimental results show that the chip area has been reduced by 46.5% and data transfer latency by 17.1%, respectively, compared to conventional architecture.
Keywords
NoC; Network interface; MPSoC;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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