• 한국재료학회지
• /
• 제17권2호
• /
• pp.61-67
• /
• 2007

The magnetron reactive sputtering was adopted to deposit CuO buffer layers on the polyimide surfaces for increasing the adhesion strength between Cu thin films and polyimide, varying $O_2$ gas flow rate from 1 to 5 sccm. The CuO oxide was formed through all the $O_2$ gas flow rates of 1 to 5 sccm, showing the highest value at the 3 sccm $O_2$ gas flow rate. The XPS analysis revealed that the $Cu_2O$ oxide was also formed with a significant ratio during the reactive sputtering. The adhesion strength is mainly dependent on the amount of CuO in the buffer layers, which can react with C-O-C or C-N bonds on the polyimide surfaces. The adhesion strength of the multi-layered Cu/buffer layer/polyimide specimen decreased linearly as the heating temperature increased to $300^{\circ}C$, even though there showd no significant change in the chemical state at the polyimide interface. This result is attributed to the decrease in surface roughness of deposited copper oxide on the polyimide, when it is heated.

• 한국결정성장학회지
• /
• 제9권2호
• /
• pp.162-167
• /
• 1999

3가지 방향성을 가진 사파이어 기판 위에 GaN 박막을 OMVPE방식으로 증착시켜 증착된 GaN epilayer를 투과전자현미경으로 분석하여 각 미세구조의 차이를 비교분석하였다. 3 가지 방향 모두에서 GaN 증착층이 관찰되어졌으며 그중 가장 좋은 경계면의 상태와 단일결정성을 보여준 것은 사파이어{0001} 방향의 기판을 사용한 경우였다. 결함들도 {0001} 방향의 기판을 사용한 경우에서 가장 적게 나타났다. 모든 경우에서 buffer layer는 발견되어지지 않았고 그럼에도 불구하고 경계면에서의 격자 뒤틀림이 일어나는 지역이 수 나노미터(nanometer) 정도밖에 안되는 우수한 경계면들이 관찰되었다. 따라서 일반적으로 GaN 박막 증착시에 가장 많이 사용되는 사파이어 basal plane 외에도 결함이 많기는 하지만, {1120}와 {1102} plane 위에도 GaN 증착층이 buffer layer 없이 증착 될 수 있다는 사실을 TEM 관찰을 통하여 알 수 있었으며 사파이어 {0001}면를 기판으로 사용한 경우에 미세구조 측면에서 볼 때 hetero-epitaxial한 GaN 박막층을 얻을 수 있는 것을 확인하였다.

• 한국세라믹학회지
• /
• 제44권12호
• /
• pp.710-714
• /
• 2007

LSGM$(La_{0.8}Sr_{0.2}Ga_{0.8}Mg_{0.2}O_{3-{\delta}})$ is the very promising electrolyte material for lower-temperature operation of SOFCs, especially when realized in anode-supported cells. But it is notorious for reacting with other cell components and resulting in the highly resistive reaction phases detrimental to cell performance. LDC$(La_{0.4}Ce_{0.6}O_{1.8})$, which is known to keep the interfacial stability between LSGM electrolyte and anode, was adopted in the anode-supported cell, and its effect on the interfacial reactivity and electrochemical performance of the cell was investigated. No severe interfacial reaction and corresponding resistive secondary phase was found in the cell with LDC buffer layer, and this is due to its ability to sustain the La chemical potential in LSGM. The cell exhibited the open circuit voltage of 0.64V, the maximum power density of 223 $mW/cm^2$, and the ohmic resistance of $0.17{\Omega}cm^2$ at $700^{\circ}C$. These values were much improved compared with those from the cell without any buffer layer, which implies that formation of the resistive reaction phases in LSGM and then deterioration of the cell performance is resulted mainly from the La diffusion from LSGM electrolyte to anode.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
• /
• pp.186-189
• /
• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
• /
• pp.183-186
• /
• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.529-530
• /
• 2006

$Bi_2Sr_2CuO_x$ thin films have been fabricated by atomic layer-by-layer deposition using the ion beam sputtering method. During the deposition, 10 and 90 wt%-ozone/oxygen mixture gas of typical pressure of $1{\sim}9{\times}10^{-5}\;Torr$ are supplied with ultraviolet light irradiation for oxidation. XRD and RHEED investigations reveal out that a buffer layer with some different compositions is formed at the early deposition stage of less than 10 units cell and then Bi-2201 oriented along the c-axis is grown.

• 한국세라믹학회지
• /
• 제32권7호
• /
• pp.793-798
• /
• 1995

The relaxation of the intrinsic stresses in the diamond films fabricated by the hot filament CVD was studied, and it was confirmed that the tensile intrinsic stresses in the films could be controlled without any degradation in the quality of the diamond films. The tensile intrinsic stresses in the films decreased from 2.97 to 1.42 GPa when the substrate thickness increased from 1 to 10mm. This result showed that the residual stress was affected by the substrate thickness as well as by the interaction between grains. Applying of ＋50 V between the W filament and the Si substrate during deposition, the tensile intrinsic stress in the film deposited at 0 V was decreased from 2.40 GPa to 0.71 GPa. Such large decrease in the tensile intrinsic stress was due to $\beta$-SiC which acted as a buffer layer for the stress relaxation. However, the application of the large voltage above ＋200V resulted in the change of quality of the diamond film, and nearly had no effect on relaxation in the tensile intrinsic stress.

• 한국지구과학회지
• /
• 제25권1호
• /
• pp.10-21
• /
• 2004

Recently, spatial data integration for geoscientific application has been regarded as an important task of various geoscientific applications of GIS. Although much research has been reported in the literature, quantitative assessment of the spatial interrelationship between input data layers and an integrated layer has not been considered fully and is in the development stage. Regarding this matter, we propose here, methodologies that account for the spatial interrelationship and spatial patterns in the spatial integration task, namely a multi-buffer zone analysis and a statistical analysis based on a contingency table. The main part of our work, the multi-buffer zone analysis, was addressed and applied to reveal the spatial pattern around geological source primitives and statistical analysis was performed to extract information for the assessment of an integrated layer. Mineral potential mapping using multi-source geoscience data sets from Ogdong in Korea was applied to illustrate application of this methodology.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제51권3호
• /
• pp.99-104
• /
• 2002

lateral insulated gate bipolar transistors(LIGBTs) are extensively used in high voltage power IC application due to their low forward voltage drops. One of the main disadvantages of the LIGBT is its scow switching speed when compared to the LDMOSFET. And the LIGBT with reverse channel structure is lower current capability than the conventional LIGBT at the forward conduction mode. In this paper, the LIGBT which included p+ ring and p-channel gate is presented at the reverie channel structure. The presented LIGBT structure is proposed to suppress the latch up, efficiently and to improve the turn off time. It is shown to improve the current capability too. It is verified 2-D simulator, MEDICI. It is shown that the latch up current of new LIGBT is 10 times than that of the conventional LIGBT Additionally, it is shown that the turn off characteristics of the proposed LIGBT is i times than that of the conventional LIGBT. It is net presented the tail current of turn off characteristics at the proposed structure. And the presented LIGBT is not n+ buffer layer because it includes p channel gate and p+ ring.

• 한국초전도저온공학회:학술대회논문집
• /
• 한국초전도저온공학회 2003년도 학술대회 논문집
• /
• pp.113-116
• /
• 2003

The growth properties of $Y_2$O$_3$ and CeO$_2$ films for the buffer layers on Ni tapes were studied comparatively. The water vapor larger than 2$\times$10$^{-5}$ Torr and the substrate temperature higher than $700^{\circ}C$ were required for the proper growth of $Y_2$O$_3$ films, while the upper limits of the water vapor and the lower limit of the substrate temperatures for the proper growth of CeO$_2$ were 1$\times$10$^{-5}$ Torr and 50$0^{\circ}C$, respectively. These imply that the windows of the growth conditions of CeO$_2$ are wider than those of $Y_2$O$_3$. However the formation of cracks in CeO$_2$ films were its disadvantage, while $Y_2$O$_3$ showed no cracks. PACS. No 85.25.K, 81.15.A.