• 반도체디스플레이기술학회지
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• 제14권4호
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• pp.72-77
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• 2015

Three-level diode clamped multilevel inverter, generally known as neutral point clamped (NPC) inverter, has an inherent problem causing neutral point (NP) potential variation. Until now, the NP potential problem of variation has been investigated and lots of solutions have also been proposed. This paper presents a neutral point voltage control technology using the anti-windup PI controller and offset technology of PWM (Pulse Width Modulation) to control the variation of NPC 3-phase three-level inverter neutral point voltage. And the proposed algorithm is tested and verified using a PLL (Phase Locked Loop) in order to synchronize the phase voltage from the line voltage of grid. It significantly improves the voltage balancing under a solar fluctuation conditions of the inverter. Experimental results show the good performance and effectiveness of the proposed method.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1203-1210
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• 2017

Switched-inductor (SL) Z-source three-level inverter is a novel high power topology. The SL based impedance network can boost the input dc voltage to a higher value than the single LC impedance network. However, as all the neutral-point-clamped (NPC) inverters, the SL Z-source three-level inverter has to balance the neutral-point (NP) potential too. The principle of the inverter is introduced and then the effects of NP potential unbalance are analyzed. A NP balancing method is proposed. Other than the methods for conventional NPC inverter without Z-source impedance network, the upper and lower shoot-through durations are corrected by the feedforward compensation factors. With the proposed method, the NP potential is balanced and the voltage boosting ability of the Z-source network is not affected obviously. Simulations are conducted to verify the proposed method.

• Journal of Power Electronics
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• 제3권4호
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• pp.205-214
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• 2003

This paper proposes a simple control strategy based on the discontinuous PWM (DPWM) to balance the DC-link voltage of three-level neutral-point-clamped (NPC) inverter at low modulation index. It introduces new DPWM methods in multi-level inverter and one of them is used for balancing the DC-link voltage. The current flowing in the neutral point of the DC-link causes the fluctuation of the DC-link voltage of the NPC inverter. The proposed DPWM method changes the path and duration time of the neutral point current, which makes the overall fluctuation of the DC-link voltage zero during a sampling time of the reference voltage vector. Therefore, by using the proposed strategy, the voltage of the DC-link can be balanced fairly well and the voltage ripple of the DC-link is also reduced significantly. Moreover, comparing with conventional methods which have to perform the complicated calculation, the proposed strategy is very simple. The validity of the proposed DPWM method is verified by the experiment.

• 전력전자학회논문지
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• 제19권5호
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• pp.407-414
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• 2014

This study proposes a control design for the grid output current and for reducing the neutral-point voltage oscillation through the small-signal modeling of the three-phase grid connected with a three-level neutral-point-clamped (NPC) inverter with LCL filter. The three-level NPC inverter presents an inherent problem: the neutral-point voltage fluctuation caused by the neutral-point current flowing in or out from the neutral point. The small signal modeling consists of averaging, dq0 transformation, perturbing, and linearizing steps performed on a three-phase grid connected to a three-level NPC inverter with LCL filter. The proposed method controls both the grid output and neutral-point currents at every switching period and reduces the neutral-point voltage oscillation. The validity of the proposed method is verified through simulation and experiment.

• 전력전자학회논문지
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• 제14권4호
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• pp.333-342
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• 2009

중성점 클램핑 방식(Neutral Point Clamped) 인버터로 알려져 있는 3레벨 NPC 인버터는 그 구조적 특성상 직류-링크(DC-link) 중성점(Neutral Point)에서 전압이 변동한다. 지금까지 많은 논문에서 이 문제에 대한 연구가 진행되었고 다양한 형태의 해결책들이 제시되었다. 그러나 인버터 내부에서 고장이 발생하여 그에 따른 고장허용제어가 NPC 인버터 시스템에 적용되었을 경우 중성점 전압변동은 정상 운전 시 나타나는 전압변동과 다르게 나타나기 때문에 고장허용 제어에 따른 중성점 전압변동에 대한 분석이 필요하다. 본 논문에서는 삼각파 비교 변조방법을 시스템에 적용하였을 경우 정상운전과 고장 발생 과 고장허용 제어 적용 시 직류-링크 중성점 전압 변동이 어떤 양상으로 나타나는지 분석하고 고장허용 제어에 의한 NPC 인버터의 고장검출 시간과 커패시터의 용량 사이의 관계를 고찰하였다. 시뮬레이션과 실험 결과를 이용하여 이론적 분석의 타당성을 검증하였다.

• Journal of Power Electronics
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• 제16권1호
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• pp.142-152
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• 2016

Common mode voltage (CMV) generation is a major problem in switching power converter fed induction motor drive systems. CMV is the zero sequence voltage generated due to the switching action of power converters. Even a small magnitude of CMV with a high rate of change may circulate large bearing currents which may damage a machine's bearings and shorten its life. There are several methods of controlling CMV. This paper presents 3-level sinusoidal pulse width modulation based techniques to control the magnitude and rate of change of CMV in multilevel AC-DC-AC drive systems. Simulation and experimental investigations have been presented to validate the performance of proposed technique to control CMV in 3-level neutral point clamped inverter based AC-DC-AC system.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 추계학술대회
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• pp.171-172
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• 2018

본 논문에서는 NPC (Neutral-Point-Clamped) 인버터와 ANPC (Active Neutral-Point-Clamped) 인버터의 특성과 성능을 비교 분석한다. ANPC 인버터는 기존의 NPC 인버터와 비교하여 스위칭 부하를 분산시켜 발열의 불균형을 해소하고 소자 수명을 증가시킨다. 기존의 NPC 인버터 시스템과 ANPC 인버터에 대하여 이론적인 특징과 성능을 분석하고 모델링과 시뮬레이션을 통하여 비교 분석한다.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.362-371
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• 2018

This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.738-750
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• 2017

In this paper, carrier-based pulse width modulation (CBPWM), space vector PWM (SVPWM) and reduced switching losses PWM (RSLPWM) for the three-level neutral point clamped (NPC) inverter are introduced. In the case of the neutral point (NP) potential (NPP) offset, an asymmetric disposition PWM (ASPDPWM) strategy is proposed, which can output PWM sequences correctly and suppress the lower order harmonics of the inverter effectively. An NPP balance strategy based on carrier based PWM (CBPWM) is analyzed. A hybrid modulation strategy combining RSLPWM and the NPP balance based on CBPWM is proposed, and hysteresis control is adopted to switch between the two modulation strategies. An experimental prototype of the three-level NPC inverter is built. The effectiveness of the hybrid modulation is verified with a resistance-inductance load and a permanent magnetic synchronous motor (PMSM) load, respectively. The experimental results show that reduced switching losses and an acceptable NPP can be effectively achieved in the hybrid modulation strategy.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.385-387
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• 2008

Three-level Diode Clamped Multilevel Inverter, generally known as Neutral-Point-Clamped(NPC) inverter, has an inherent problem causing Neutral Point(NP) potential variation. Until now, in many literatures NP potential problem has been investigated and lots of solutions have also been proposed. However, in the case of NP potential variation was rarely published from the standpoint of reliability. In this paper, NP potential is analytically investigated both normal and fault conditions under carrier based PWM. Subsequently, relation between fault detection time and size of capacitor is analyzed. This information is explored by simulation results, which contribute to enhance the reliability of the NPC inverter system.