• Journal of Power Electronics
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• 제16권1호
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• pp.142-152
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• 2016

Common mode voltage (CMV) generation is a major problem in switching power converter fed induction motor drive systems. CMV is the zero sequence voltage generated due to the switching action of power converters. Even a small magnitude of CMV with a high rate of change may circulate large bearing currents which may damage a machine's bearings and shorten its life. There are several methods of controlling CMV. This paper presents 3-level sinusoidal pulse width modulation based techniques to control the magnitude and rate of change of CMV in multilevel AC-DC-AC drive systems. Simulation and experimental investigations have been presented to validate the performance of proposed technique to control CMV in 3-level neutral point clamped inverter based AC-DC-AC system.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.489-500
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• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• Journal of Power Electronics
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• 제19권1호
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• pp.99-107
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• 2019

This study proposes a new modulation strategy to deal with unbalanced output voltage that is based on three-level neutral-point-clamped cascaded rectifiers. The fundament idea is to reallocate the value of the voltage levels generated by each of the modules on the basis of space vector pulse width modulation. This proposed modulation strategy can reduce the switching frequency while maintaining the mutual-module voltage balance. First, an analysis of unbalanced output voltage is reflected. Then a new modulation strategy is introduced in detail. Internal module capacitor voltages are balanced by the selection of redundant vectors. Moreover, the voltage balance ability is calculated. Finally, the feasibility of this modulation strategy is verified through experimental results.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.362-371
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• 2018

This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.

• Journal of Power Electronics
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• 제19권1호
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• pp.79-88
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• 2019

The neutral-point (NP) voltage of three-phase three-level NP-clamped converters is needed for balance. To maintain NP potential and suppress ripple, a novel NP voltage balancing strategy is proposed in this work. The mechanism of NP voltage variation is studied first. Then, the relationship between the disassembly of zero level (O level) and NP current is studied comprehensively. On these bases, two methods for selecting one of three output phases for the disassembly of its O level are presented. Finally, simulation and experimental results verify the validity and practicability of the proposed algorithms.

• Journal of Power Electronics
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• 제14권3호
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• pp.519-530
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• 2014

A novel simplified pulse width modulation(PWM) strategy for neutral point clamped (NPC) three-level converter is proposed in this paper.The direct output voltage modulation is applied to reduce the calculation time. Based on this strategy, several optimized control methods are proposed. The neutral point potential balancing algorithm is discussed and a fine neutral point potential balancing scheme is introduced. Moreover, the minimum pulse width compensation and switching losses reduction can be easily achieved using this modulation strategy. This strategy also gains good results even with the unequal DC link capacitor. The modulation principle is studied in detail and the validity of this simplified PWM strategy is experimentally verified in this paper. The experiment results indicated that the proposed PWM strategy has excellent performance, and the neutral point potential can be balanced well with unequal DC link captaincies.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.738-750
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• 2017

In this paper, carrier-based pulse width modulation (CBPWM), space vector PWM (SVPWM) and reduced switching losses PWM (RSLPWM) for the three-level neutral point clamped (NPC) inverter are introduced. In the case of the neutral point (NP) potential (NPP) offset, an asymmetric disposition PWM (ASPDPWM) strategy is proposed, which can output PWM sequences correctly and suppress the lower order harmonics of the inverter effectively. An NPP balance strategy based on carrier based PWM (CBPWM) is analyzed. A hybrid modulation strategy combining RSLPWM and the NPP balance based on CBPWM is proposed, and hysteresis control is adopted to switch between the two modulation strategies. An experimental prototype of the three-level NPC inverter is built. The effectiveness of the hybrid modulation is verified with a resistance-inductance load and a permanent magnetic synchronous motor (PMSM) load, respectively. The experimental results show that reduced switching losses and an acceptable NPP can be effectively achieved in the hybrid modulation strategy.

• Journal of Power Electronics
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• 제19권1호
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• pp.119-133
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• 2019

Although the dual modulation wave method can solve the low-frequency neutral point potential (NPP) fluctuation problem for three-level neutral point clamped converters, it also increases the switching frequency and limits the zero-sequence voltage. That makes it harmful when dealing with the NPP drift problem if the converter suffers from a long dead time or asymmetric loads. By introducing two degrees of freedom (2-DOF), an NPP control based on a search optimization method can demonstrate its ability to cope with the above mentioned two types of NPP problems. However, the amount of calculations for obtaining an optimal 2-DOF is so large that the method cannot be applied to certain industrial applications with an inexpensive digital signal processor. In this paper, a novel optimal 2-DOF-based NPP control is proposed. The relationships between the NPP and the 2-DOF are analyzed and a method for directly determining the optimal 2-DOF is also discussed. Using a direct calculation method, the amount of calculations is significantly reduced. In addition, the proposed method is able to maintain the strongest control ability for the two types of NPP problems. Finally, some experimental results are given to confirm the validity and feasibility of the proposed method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.385-387
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• 2008

Three-level Diode Clamped Multilevel Inverter, generally known as Neutral-Point-Clamped(NPC) inverter, has an inherent problem causing Neutral Point(NP) potential variation. Until now, in many literatures NP potential problem has been investigated and lots of solutions have also been proposed. However, in the case of NP potential variation was rarely published from the standpoint of reliability. In this paper, NP potential is analytically investigated both normal and fault conditions under carrier based PWM. Subsequently, relation between fault detection time and size of capacitor is analyzed. This information is explored by simulation results, which contribute to enhance the reliability of the NPC inverter system.

• Journal of Power Electronics
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• 제19권4호
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• pp.944-955
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• 2019

In this paper, the three-level T-type neutral-point-clamped indirect matrix converter topology and the relative space vector modulation methods are introduced to improve the voltage transfer ratio and output voltage performance. The presented converter topology is based on combinations of cascaded-rectifier and three-level T-type neutral-point-clamp inverter. It can overcome the limitation of voltage transfer ratio of the conventional matrix converter and the high voltage rating of power switches of conventional matrix converter. Two SVPWM strategies for proposed converter are described in this paper to achieve the advantages features such as: sinusoidal input/output currents and three-level output voltage waveforms. Results from Psim 9.0 software simulation are provided to confirm the theoretical analysis. Hence, a laboratory prototype was implemented, and the experimental results are shown to validate the simulation results and to verify the effectiveness of the proposed topology and modulation strategies.