• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.432-436
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• 2009

This paper is described that advanced study on network design of remote diagnosis system for power facilities of electric railway. In the field, it is very difficult for worker to diagnosis power facilities including catenary because workers should be maintenance on AC power supply. Therefore, to properly design on remote diagnosis system, we have searched the inside and outside of the country-related technology trends. Also we confirmed that required technologies to design interface technology required for the development of sensor devices and the USN network was designed in accordance with required skills. Throughout variety of requirements, we have development iRFS based ZA sensors and iRFM to receive data of sensor. Also CC2420 is applied as single-chip which used 2.4GHz IEEE802.15.4 compliant RF tranciver designed for low-power and low-voltage wireless applications for ZigBee communication.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.9-15
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• 2006

This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

• Journal of applied mathematics & informatics
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• v.28 no.1_2
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• pp.539-551
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• 2010

Low scalability and power efficiency of the shared bus in SoCs is a motivation to use on chip networks instead of traditional buses. In this paper we have modified the Orion power model to reach an analytical model to estimate the average message energy in K-Ary n-Cubes with focus on the number of virtual channels. Afterward by using the power model and also the performance model proposed in [11] the effect of number of virtual channels on Energy-Delay product have been analyzed. In addition a cycle accurate power and performance simulator have been implemented in VHDL to verify the results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.29-37
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• 2006

This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize the resonance effects, the resonance frequency of the circuit is accurately estimated in an analytical manner. Thereby, a decoupling capacitor size to suppress the resonance for a suitable circuit operation is accurately determined by using the estimated resonance frequency. The developed novel design methodology is verified by using $0.18{\mu}m$ process-based-HSPICE simulation.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.1
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• pp.60-65
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• 2006

Recently, various ubiquitous networking services are developed and implemented for easy living. In general, new ubiquitous networking services require the new infrastructure including equipments and devices. However, it is difficult to replace existing infrastructure and devices with new ones in the home or office because of cost and maintenance problems. In this paper, we developed small-size web based RF wireless communication systems for sensor network applications. The designed RF systems are implemented using commercial system on a chip (SoC) on existing infrastructure and devices. The developed systems are tested for light control and temperature sensing and they are applied to sensor network training courses for students and engineer as well as various practical applications.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.1-8
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• 1995

In this paper, we propose an extendible copy network in a large-scale ATM switch consisting of small switch modules implementable on a single VLSI chip or a single PCB. Considering multicasting switches consist of a copy network and a routing network, there exist broadcast and group translators (BGT) which assign the destination addresses into copied cells. The BGT table can be reduced by vertical partitioning method; copied cells are translated in adjacent BGTs and each BGT table has a single destination address per connection. In addition, the distribution network routes and copies incomming cells into several groups statically which are translated into consecutive BGTs. This guarantees the integrity of cell sequences. Connection-setup time as well as the BGT table size can be reduced significantly.

• ETRI Journal
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• v.42 no.4
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• pp.491-504
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• 2020

We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on-chip memory. Complementing the hardware is an intuitive and user-friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40-TFLOP STC that includes 32k arithmetic units and over 36 MB of on-chip SRAM, our baseline implementation of AB9 consists of a 1-GHz quad-core setup with other various industry-standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general-purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28-nm process with a chip size of 17 × 23 ㎟. Delivery is expected later this year.

• ETRI Journal
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• v.30 no.1
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• pp.129-140
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• 2008

In this paper, we propose a novel ant colony optimization (ACO)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip (SoCs), on the assumption that the test platform, including specific methods and configurations such as test packet routing, generation, and absorption, is installed. The ACO metaheuristic model, inspired by the ant's foraging behavior, can autonomously find better results by exploring more solution space. The proposed method efficiently combines the rectangle packing method with ACO and improves the scheduling results by dynamically choosing the test-access-mechanism widths for cores and changing the testing orders. The power dissipation and variable test clock mode are also considered. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce overall test time. Moreover, the computation time of the algorithm is less than a few seconds in most cases.

• Journal of the Korean Ceramic Society
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• v.29 no.12
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• pp.956-962
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• 1992

The predominant sintering mechanisms of low firing temperature ceramic substrate which consists of borosilicate glass containing alumina as a filler are the rearrangement of alumina particles and the viscous flow of glass powders. In this system, sintering condition depends on the volume ratio of alumina to glass and on the particle size. When the substrate contains about 35 vol% alumina filler and the average alumina particle size is 4 $\mu\textrm{m}$, the best firing condition is obtained at the temperature range of 900∼1000$^{\circ}C$. The extensive rearrangement behavior occurs at these conditions, and the optimum sintering condition is attained by smaller size of glass particles, too. The formation of cristobalite during sintering causes the difference of thermal expansion coefficient between the substrate and Si chip. This phenomenon degradates the capacity of Si chip. Therefore, the crystallization should be prevented. In the alumina filled borosilicate glass system, the crystallization does not occur. This effect may have some relation with aluminum ions in alumina. For aluminum ions diffuse into glass matrix during sintering, functiong as network former.