• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.2
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• pp.129-135
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• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• Journal of the Korean Electrochemical Society
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• v.6 no.2
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• pp.153-157
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• 2003

A hybrid electrochemical capacitor having both characteristics of electric double layer capacitance and pseudo-capacitance was studied throughout cell tests. Asymmetric electrodes with $Ni(OH)_2/activated$ carbon based positive electrode and activated carbon based negative electrode were used in preparing test cells of $5\times5cm^2$. Cyclic voltammetry measurements and impedance measurements were conducted to understand electrochemical behavior of each electrode. To find an optimal mass ratio of negative to positive electrode, charge-discharge cycle tests were also performed.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.293-296
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• 2016

Using capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements, the electrical properties of Cu/n-InP Schottky diodes were investigated. The values of C and G/ω were found to decrease with increasing frequency. The presence of interface states might cause excess capacitance, leading to frequency dispersion. The negative capacitance was observed under a forward bias voltage, which may be due to contact injection, interface states or minority-carrier injection. The barrier heights from C-V measurements were found to depend on the frequency. In particular, the barrier height at 200 kHz was found to be 0.65 eV, which was similar to the flat band barrier height of 0.66 eV.

• Transactions on Electrical and Electronic Materials
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• v.14 no.4
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• pp.177-181
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• 2013

In this paper, silicon solar cells are analyzed regarding power conversion efficiency by changed capacitance in the depletion region. For the capacitance control in the depletion region of silicon solar cell was applied for 10, 20, 40, 80, 160 and 320 Hz frequency band character and alternating current(AC) voltage with square wave of 0.2~1.4 V. Academically, symmetry formation of positive and negative change of the p-n junction is similar to the physical effect of capacitance. According to the experiment result, because input of square wave with alternating current(AC) voltage could be observed to changed capacitance effect by indirectly method through non-linear power conversion (Voltage-Current) output. In addition, when input alternating current(AC) voltage in the silicon solar cell, changed capacitance of depletion region with the forward bias condition and reverse bias condition gave a direct effect to the charge mobility.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.6
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• pp.817-820
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• 2012

We studied p-type capacitance characteristics of ZnO thin-film transistors (TFT's), grown by metal organic chemical vapor deposition (MOCVD). We compared two ZnO TFT's: one grown at $450^{\circ}C$ and the other grown at $350^{\circ}C$. ZnO grown at $450^{\circ}C$ showed smooth capacitance profile with electron density of $1.5{\times}10^{20}cm^{-3}$. In contrast, ZnO grown at $350^{\circ}C$ showed a capacitance jump when gate voltage was changed to negative voltages. Current-voltage characteristics measured in the two samples did not show much difference. We explain that the capacitance jump is related to p-type ZnO layer formed at the $SiO_2$ interface. Current-voltage and capacitance-voltage data support that p-type characteristics are observed only when background electron density is very low.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.179-182
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• 2003

A simulation on bootstrapping circuit has been performed by modelling a coaxial cable as a transmission line. It is shown that the bootstrapping circuit could be unstable due to the transmission line effect though an ideal amplifier is used. While the conventional bootstrapping circuit does not cancel the input capacitance of the input buffer, a new bootstrapping circuit that cancels input capacitance of the input buffer has been proposed. The proposed bootstrapping circuit consists of the input buffer of which gam is larger than 1 and a feedback resistor to control the loop gain. The proposed bootstrapping circuit has higher input impedance than that of the conventional circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• International Journal of Aeronautical and Space Sciences
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• v.15 no.4
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• pp.396-411
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• 2014

Synchronized switch damping (SSD) techniques have recently been developed for structural vibration control using piezoelectric materials. In these techniques, piezoelectric materials are bonded on the vibrating structure and shunted by a network of electrical elements. These piezoelectric materials are switched according to the amplitude of the excitation force to damp vibration. This paper presents a new SSD technique called 'synchronized switch damping on negative capacitance and adaptive voltage sources' (SSDNCAV). The technique combines the phenomenon of capacitance transient charging and electrical resonance to effectively dampen the structural vibration. Also, the problem of stability observed in the previous SSD techniques is effectively addressed by adapting the voltage on the piezoelectric patch according to the vibration amplitude of the structure. Analytical expressions of vibration attenuation at the resonance frequency are derived, and the effectiveness of this new technique is demonstrated, for the control of a resonant cantilever beam with bonded piezoelectric patches, by comparing with SSDI, SSDVenh, and SSDNC techniques. Theoretical predictions and experimental results show the remarkable vibration damping capability of SSDNCAV technique, which was better than the previous SSD techniques. The broadband vibration control capabilities of SSDNCAV technique are also demonstrated, which exceed those of previous SSD techniques.

• Journal of IKEEE
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• v.22 no.1
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• pp.209-212
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• 2018

In this work, we developed P(VDF-TrFE) organic/ferroelectric material based metal-ferroelectric-metal (MFM) capacitors in order to improve the switching characteristics of gallium nitride (GaN) heterojunction field-effect transistors (HFET). The 27 nm-thick P(VDF-TrFE) MFM capacitors exhibited about 60 ~ 96 pF capacitance with a polarization density of $6{\mu}C/cm^2$ at 4 MV/cm. When the MFM capacitor was connected in series with the gate electrode of GaN HFET, the subthreshold slope decreased from 104 to 82 mV/dec.