• 한국전기전자재료학회논문지
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• 제36권2호
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• pp.129-135
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• 2023

An analytical threshold voltage model is presented to observe the change in threshold voltage shift ΔV_th of a junctionless double gate MOSFET using ferroelectric-metal-SiO₂ as a gate oxide film. The negative capacitance transistors using ferroelectric have the characteristics of increasing on-current and lowering off-current. The change in the threshold voltage of the transistor affects the power dissipation. Therefore, the change in the threshold voltage as a function of theferroelectric thickness is analyzed. The presented threshold voltage model is in a good agreement with the results of TCAD. As a results of our analysis using this analytical threshold voltage model, the change in the threshold voltage with respect to the change in the ferroelectric thickness showed that the threshold voltage increased with the increase of the absolute value of charges in the employed ferroelectric. This suggests that it is possible to obtain an optimum ferroelectric thickness at which the threshold voltage shift becomes 0 V by the voltage across the ferroelectric even when the channel length is reduced. It was also found that the ferroelectric thickness increased as the silicon thickness increased when the channel length was less than 30 nm, but the ferroelectric thickness decreased as the silicon thickness increased when the channel length was 30 nm or more in order to satisfy ΔV_th=0.

• 전기화학회지
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• 제6권2호
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• pp.153-157
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• 2003

전기이중층 축전용량(electric double layer capacitance)과 유사축전용량(pseudo-capacitance)을 함께 갖는 하이브리드 전기화학 축전기에 대한 연구를 수행하였다. 양극은 $Ni(OH)_2$ 활성탄소가 복합된 전극을 사용하였으며 음극은 활성탄소를 활물질로 사용하므로써 비대칭 전극 구조를 갖는다. 셀 실험을 위하여 $5\times5cm^2$ 크기인 전극을 제작 사용하였다. Cyclic voltammetry측정 및 교류 임피던스 측정실험을 통하여 각각의 셀들이 갖는 전기화학적 거동을 조사하였고 충 방전 실험을 통하여 양극과 음극의 최적 질량비를 조사하였다.

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.293-296
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• 2016

Using capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements, the electrical properties of Cu/n-InP Schottky diodes were investigated. The values of C and G/ω were found to decrease with increasing frequency. The presence of interface states might cause excess capacitance, leading to frequency dispersion. The negative capacitance was observed under a forward bias voltage, which may be due to contact injection, interface states or minority-carrier injection. The barrier heights from C-V measurements were found to depend on the frequency. In particular, the barrier height at 200 kHz was found to be 0.65 eV, which was similar to the flat band barrier height of 0.66 eV.

• Transactions on Electrical and Electronic Materials
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• 제14권4호
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• pp.177-181
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• 2013

In this paper, silicon solar cells are analyzed regarding power conversion efficiency by changed capacitance in the depletion region. For the capacitance control in the depletion region of silicon solar cell was applied for 10, 20, 40, 80, 160 and 320 Hz frequency band character and alternating current(AC) voltage with square wave of 0.2~1.4 V. Academically, symmetry formation of positive and negative change of the p-n junction is similar to the physical effect of capacitance. According to the experiment result, because input of square wave with alternating current(AC) voltage could be observed to changed capacitance effect by indirectly method through non-linear power conversion (Voltage-Current) output. In addition, when input alternating current(AC) voltage in the silicon solar cell, changed capacitance of depletion region with the forward bias condition and reverse bias condition gave a direct effect to the charge mobility.

• 전기학회논문지
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• 제61권6호
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• pp.817-820
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• 2012

We studied p-type capacitance characteristics of ZnO thin-film transistors (TFT's), grown by metal organic chemical vapor deposition (MOCVD). We compared two ZnO TFT's: one grown at $450^{\circ}C$ and the other grown at $350^{\circ}C$. ZnO grown at $450^{\circ}C$ showed smooth capacitance profile with electron density of $1.5{\times}10^{20}cm^{-3}$. In contrast, ZnO grown at $350^{\circ}C$ showed a capacitance jump when gate voltage was changed to negative voltages. Current-voltage characteristics measured in the two samples did not show much difference. We explain that the capacitance jump is related to p-type ZnO layer formed at the $SiO_2$ interface. Current-voltage and capacitance-voltage data support that p-type characteristics are observed only when background electron density is very low.

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.179-182
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• 2003

A simulation on bootstrapping circuit has been performed by modelling a coaxial cable as a transmission line. It is shown that the bootstrapping circuit could be unstable due to the transmission line effect though an ideal amplifier is used. While the conventional bootstrapping circuit does not cancel the input capacitance of the input buffer, a new bootstrapping circuit that cancels input capacitance of the input buffer has been proposed. The proposed bootstrapping circuit consists of the input buffer of which gam is larger than 1 and a feedback resistor to control the loop gain. The proposed bootstrapping circuit has higher input impedance than that of the conventional circuit.

• 한국정보전자통신기술학회논문지
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• 제13권2호
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• pp.123-128
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• 2020

본 논문에서는 주파수 변화 감지 회로 (FVSC : frequency variation sensing circuit)를 포함하는 부궤환 루프를 가지는 저잡음 위상고정루프를 제안하였다. 위상 고정 상태에서 전압제어발진기의 출력주파수가 변화할 때 주파수 변화 감지 회로는 루프 필터의 커패시터의 전하량을 조절하여 제안한 위상고정루프의 위상잡음과 지터 특성을 개선할 수 있다. 위상고정루프의 출력 주파수가 증가하면 주파수 변화 감지 회로가 루프 필터 커패시터 전하를 감소시킨다. 이는 루프필터 출력 전압을 하강하게 하여 위상고정루프 출력 주파수가 하강하게 된다. 추가된 부궤환 루프는 제안한 위상고정루프의 위상잡음 특성을 더욱 더 좋게 한다. 주파수 변화 감지 회로에 사용된 커패시터 크기는 영점을 결정하는 루프 필터 커패시터 크기와 비교하여도 아주 작은 크기이어서 칩 크기에 영향을 미치지 않는다. 제안된 저잡음 위상고정루프는 1.8V 0.18㎛ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 273fs 지터와 1.5㎲ 위상고정시간을 보여주었다.

• International Journal of Aeronautical and Space Sciences
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• 제15권4호
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• pp.396-411
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• 2014

Synchronized switch damping (SSD) techniques have recently been developed for structural vibration control using piezoelectric materials. In these techniques, piezoelectric materials are bonded on the vibrating structure and shunted by a network of electrical elements. These piezoelectric materials are switched according to the amplitude of the excitation force to damp vibration. This paper presents a new SSD technique called 'synchronized switch damping on negative capacitance and adaptive voltage sources' (SSDNCAV). The technique combines the phenomenon of capacitance transient charging and electrical resonance to effectively dampen the structural vibration. Also, the problem of stability observed in the previous SSD techniques is effectively addressed by adapting the voltage on the piezoelectric patch according to the vibration amplitude of the structure. Analytical expressions of vibration attenuation at the resonance frequency are derived, and the effectiveness of this new technique is demonstrated, for the control of a resonant cantilever beam with bonded piezoelectric patches, by comparing with SSDI, SSDVenh, and SSDNC techniques. Theoretical predictions and experimental results show the remarkable vibration damping capability of SSDNCAV technique, which was better than the previous SSD techniques. The broadband vibration control capabilities of SSDNCAV technique are also demonstrated, which exceed those of previous SSD techniques.

• 전기전자학회논문지
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• 제22권1호
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• pp.209-212
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• 2018

본 논문에서는 P(VDF-TrFE)유기물 강유전체 기반 metal-ferroelectric-metal (MFM) capacitor 와 차세대 반도체 물질인 질화갈륨 반도체를 활용한 네거티브 커패시턴스 전계효과 트랜지스터를 제작 및 분석 하였다. 27 nm의 두께의 P(VDF-TrFE) MFM 커패시터의 분극지수는 4 MV/cm에서 $6{\mu}C/cm^2$ 값을 나타내었으며 약 65 ~ 95 pF의 커패시턴스 값을 나타내었다. 강유전체의 커패시턴스와 전계효과 트랜지스터의 커패시턴스 매칭을 분석하기 위해 제작된 P(VDF-TrFE) MFM 커패시터는 GaN 전계효과 트랜지스터의 게이트 전극에 집적화 되었으며 집적화되기 전 104 mV/dec 의 문턱전압 이하 기울기에서 82 mV/dec 값으로 개선된 효과를 보였다.