• Title/Summary/Keyword: Nanowire electronics

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Fabrication of Metal Nanobridge Arrays using Sacrificial Silicon Nanowire

  • Lee, Kook-Nyung;Lee, Kyoung-Gun;Jung, Suk-Won;Lee, Min-Ho;Seong, Woo-Kyeong
    • Journal of Electrical Engineering and Technology
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    • v.7 no.3
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    • pp.396-400
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    • 2012
  • Novel fabrication method of nanobridge array of various materials was proposed using suspended silicon nanowire array as a sacrificial template structure. Nanobridges of various materials can be simply fabricated by direct deposition with thermal evaporation on the top of prefabricated suspended silicon nanobridge arrays, which are used as a sacrificial structure. Since silicon nanowire can be easily removed by selective dry etching, nanobridge arrays of an intended material are finally obtained. In this paper, metal nanobridges of Ti/Au, around 50-200 nm in thickness and width, 5-20 ${\mu}m$ in length were fabricated to prove the advantages of the proposed nanowire or nanobridge fabrication method. The nanobridges of Ti/Au after complete removal of sacrificial silicon nanowire template were well-established and bending of nanobridge caused by the tensile stress was observed after silicon removing. Up to 50 nm and 10 ${\mu}m$ of silicon nanowire in diameter and length respectively was also very useful for nanowire templates.

Fabrication of Large-Scale Single-Crystal Organic Nanowire Arrays for High-Integrated Flexible Electronics

  • Park, Gyeong-Seon;Seong, Myeong-Mo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.266.1-266.1
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    • 2013
  • Large-scale single-crystal organic nanowire arrays were generated using a direct printing method (liquidbridge- mediated nanotransfer molding) that enables the simultaneous synthesis, alignment and patterning of nanowires from molecular ink solutions. Using this method, single-crystal organic nanowires can easily be synthesized by self-assembly and crystallization of organic molecules within the nanoscale channels of molds, and these nanowires can then be directly transferred to specific positions on substrates to generate nanowire arrays by a direct printing process. Repeated application of the direct printing process can be used to produce organic nanowire-integrated electronics with two- or three-dimensional complex structures on large-area flexible substrates. This efficient manufacturing method is used to fabricate all-organic nanowire field-effect transistors that are integrated into device arrays and inverters on flexible plastic substrates.

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The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation

  • Yang, Seung-Dong;Oh, Jae-Sub;Yun, Ho-Jin;Jeong, Kwang-Seok;Kim, Yu-Mi;Lee, Sang Youl;Lee, Hi-Deok;Lee, Ga-Won
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.3
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    • pp.139-142
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    • 2013
  • Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

Analytical Threshold Voltage Modeling of Surrounding Gate Silicon Nanowire Transistors with Different Geometries

  • Pandian, M. Karthigai;Balamurugan, N.B.
    • Journal of Electrical Engineering and Technology
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    • v.9 no.6
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    • pp.2079-2088
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    • 2014
  • In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

All-Organic Nanowire Field-Effect Transistors and Complementary Inverters Fabricated by Direct Printing

  • Park, Gyeong-Seon;Seong, Myeong-Mo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.632-632
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    • 2013
  • We generated single-crystal organic nanowire arrays using a direct printing method (liquidbridge- mediated nanotransfer molding) that enables the simultaneous synthesis, alignment and patterning of nanowires from molecular ink solutions. Using this method, single-crystal organic nanowires can easily be synthesized by self-assembly and crystallization of organic molecules within the nanoscale channels of molds, and these nanowires can then be directly transferred to specific positions on substrates to generate nanowire arrays by a direct printing process. The position of the nanowires on complex structures is easy to adjust, because the mold is movable on the substrates before the polar liquid layer, which acts as an adhesive lubricant, is dried. Repeated application of the direct printing process can be used to produce organic nanowire-integrated electronics with twoor three-dimensional complex structures on large-area flexible substrates. This efficient manufacturing method is used to fabricate all-organic nanowire field-effect transistors that are integrated into device arrays and inverters on flexible plastic substrates.

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A Study on the Electrical Characterization of Top-down Fabricated Si Nanowire ISFET (Top-down 방식으로 제작한 실리콘 나노와이어 ISFET 의 전기적 특성)

  • Kim, Sungman;Cho, Younghak;Lee, Junhyung;Rho, Jihyoung;Lee, Daesung
    • Journal of the Korean Society for Precision Engineering
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    • v.30 no.1
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    • pp.128-133
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    • 2013
  • Si Nanowire (Si-NW) arrays were fabricated by top-down method. A relatively simple method is suggested to fabricate suspended silicon nanowire arrays. This method allows for the production of suspended silicon nanowire arrays using anisotropic wet etching and conventional MEMS method of SOI (Silicon-On-Insulator) wafer. The dimensions of the fabricated nanowire arrays with the proposed method were evaluated and their effects on the Field Effect Transistor (FET) characteristics were discussed. Current-voltage (I-V) characteristics of the device with nanowire arrays were measured using a probe station and a semiconductor analyzer. The electrical properties of the device were characterized through leakage current, dielectric property, and threshold voltage. The results implied that the electrical characteristics of the fabricated device show the potential of being ion-selective field effect transistors (ISFETs) sensors.

Threshold and Flat Band Voltage Modeling and Device design Guideline in Nanowire Junctionless Transistors (나노와이어 junctionless 트랜지스터의 문턱전압 및 평탄전압 모델링과 소자설계 가이드라인)

  • Kim, Jin-Young;Yu, Chong-Gun;Park, Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.12
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    • pp.1-7
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    • 2011
  • In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.

Fabrication of Organic Nanowire Electronics by Direct Printing Method

  • Park, Gyeong-Seon;Seong, Myeong-Mo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.563-563
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    • 2012
  • We report a one-step fabrication of single-crystal organic nanowire arrays on substrates using a new direct printing method (liquid-bridge-mediated nanotransfer moulding, LB-nTM), which can simultaneously enable the synthesis, alignment and patterning of the nanowires using molecular ink solutions. Two- or three-dimensional complex structures of various single-crystal organic nanowires were directly fabricated over a large area with a successive process. The position of the nanowires can be aligned easily on complex structures because the mold is movable on substrates before drying the polar liquid layer, which acts as an adhesive lubricant. This efficient manufacturing method can produce a wide range of optoelectronic devices and integrated circuits with single-crystal organic nanowires.

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Nanoscale Floating-Gate Characteristics of Colloidal Au Nanoparticles Electrostatically Assembled on Si Nanowire Split-Gate Transistors

  • Jeon, Hyeong-Seok;Park, Bong-Hyun;Cho, Chi-Won;Lim, Chae-Hyun;Ju, Heong-Kyu;Kim, Hyun-Suk;Kim, Sang-Sig;Lee, Seung-Beck
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.2
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    • pp.101-105
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    • 2006
  • Nanoscale floating-gate characteristic of colloidal Au nanoparticles electrostatically assembled on the oxidized surface of Si nanowires have been investigated. The Si nanowire split-gate transistor structure was fabricated by electron beam lithography and subsequent reactive ion etching. Colloidal Au nanoparticles with ${\sim}5$ nm diameters were selectively deposited onto the Si nanowire surface by 2 min electrophoresis. It was found that electric fields applied to the self-aligned split side gates allowed charge to be transferred on the Au nanoparticles. It was observed that the depletion mode cutoff voltage, induced by the self-aligned side gates, was shifted by more than 1 V after Au nanoparticle electrophoresis. This may be due to the semi-one dimensional nature of the narrow Si nanowire transport channel, having much enhanced sensitivity to charges on the surface.

Estimation of Sensitivity Enhancements of Material-Dependent Localized Surface Plasmon Resonance Sensor Using Nanowire Patterns (금속물질에 따른 나노구조를 이용한 국소 표면 플라즈몬 공명 센서 특성 분석)

  • Ahn, Heesang;Ahn, Dong-Gyu;Song, Yung Min;Kim, Kyujung
    • Journal of the Korean Society for Precision Engineering
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    • v.33 no.5
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    • pp.363-369
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    • 2016
  • We explored localized plasmonic field enhancements using nanowire patterns to improve the sensitivity of a surface plasmon resonance (SPR) sensor. Two different materials, gold and silver, were considered for sample materials. Gold and silver nanowire patterns were fabricated by electron beam lithography for experimental measurements. The wavelength SPR sensor was also designed for these experiments. The material-dependent field enhancements on nanowire patterns were first calculated based on Maxwell's equations. Resonance wavelength shifts were indicated as changes in the refractive index from 1.33 to 1.36. The SPR sensor with silver nanowire patterns showed a much larger resonance wavelength shift than the sensor with gold nanowire patterns, in good agreement with simulation results. These results suggest that silver nanowire patterns are more efficient than gold nanowire patterns, and could be used for sensitivity enhancements in situations where biocompatibility is not a consideration.