• 센서학회지
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• 제16권6호
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• pp.475-483
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• 2007

This paper proposes a readout integrated circuit (ROIC) for $32{\times}32$ infrared focal plane array (IRFPA) detector, which consist of reference resistor, detector resistor, reset switch, integrated capacitor and operational amplifier. Proposed ROIC is designed using $0.35{\;}{\mu}m$ 2P-4M (double poly four metal) n-well CMOS process parameters. Low noise folded cascode operational amplifier which is a key element in the ROIC showed 12.8 MHz unity-gain bandwidth and open-gain 89 dB, phase margin $67^{\circ}$, SNR 82 dB. From proposed circuit, we gained output voltage variation ${\Delta}17{\};mV/^{\circ}C$ when the detector resistor varied according to the temperature.

• 한국산학기술학회논문지
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• 제11권12호
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• pp.4984-4990
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• 2010

기존의 DC-DC Converter에서는 전압 변화 및 에너지 축적소자로서 자성부품인 인덕터를 사용하여 자속 발생에 의한 전력 손실로 효율이 낮아지고, 자성부품의 부피가 크고 무거우며 가격이 비싸 반도체 칩으로 집적화하기에 문제점을 가지고 있다. 이러한 문제점을 개선하기 위해 본 논문에서는 인덕터없는 스위치드 커패시터 방식을 이용한 저전력 강압형 CMOS DC-DC Converter를 제안한다. 제안된 DC-DC Converter는 0.5um 공정을 이용하여 설계하였으며, 설계된 DC-DC 컨버터는 200kHz의 주파수로 동작하며 96%이상의 전력효율을 cadence 시뮬레이션을 통하여 얻을 수 있다.

• 전기전자학회논문지
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• 제18권2호
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• pp.228-233
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• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• 한국산학기술학회논문지
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• 제17권6호
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• pp.715-720
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• 2016

본 논문에서는, 휴대기기를 위한 PWM(Pulse Width Modulation), 전압모드 DC-DC 승압형 컨버터를 제안한다. 제안하는 컨버터는 현재 소형화 되어가고 있는 휴대기기 시장에 적합하도록 1 MHz의 스위칭 주파수를 사용하여 칩 면적을 줄였다. 제안하는 DC-DC 컨버터는 전력단과 제어단으로 이루어지며 전력단은 인덕터, 출력 커패시터, MOS 트랜지스터 등으로 구성되며 제어단은 연산증폭기, 밴드갭 회로, 소프트 스타트 블록, 히스테리시스 비교기와 비겹침 드라이버로 구성된다. 설계된 회로는 히스테리시스 비교기와 논오버랩 드라이버를 사용하여 낮은 전압에서 구동되는 휴대기기의 잡음의 영향을 줄이고 출력전압 리플을 감소시켰다. 제안하는 회로는 1-poly 6-metal CMOS 매그나칩/하이닉스 $0.18{\mu}m$ 공정을 사용하여 레이아웃을 진행하였다. 설계된 컨버터는 입력 전압 3.3 V, 출력전압 5 V, 출력전류 100 mA 출력전압 대비 1%의 출력 전압 리플과 1 MHz의 스위칭 주파수의 특성을 갖는다. 본 논문에서 제안하는 승압형 DC-DC 컨버터는 PDA, 휴대폰, 노트북 등 휴대용 전자기기 시장에 맞는 고효율, 소형화 컨버터로서 유용하게 사용 될 것으로 사료된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.139-141
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• 2006

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nano-electronic devices which will inherit the throne of CMOS which is the domineering implementation technology of large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors. After the gate and interconnect structures of the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit QCA adder. The digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• 센서학회지
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• 제18권1호
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• pp.77-85
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• 2009

We propose a new image pixel architecture which has OFD(Over Flow Device) node by improving conventional 3TR pixel structure. Newly designed pixel consists of photo diode which is verified with HSPICE simulation, PMOS reset transistor, several NMOS and several PMOS transistors. Photodiode signals from each PMOS and NMOS are detected by Reset PMOS. These output signals give enough chances to detect wide operation coverage because OFD node has overflow photocurrent. According to various light intensity, we analyzed characteristic of the output voltage with a SPICE tool. Proposed pixel output has specific value which can detect possible from $0.1{\mu}W/cm^2$ to $10W/cm^2$ light intensity. It has wide-dynamic range of 160 dB.

• 센서학회지
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• 제17권1호
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• pp.35-40
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• 2008

Low power bridge type micro gas sensors were fabricated by micro machining technology with TMAH (Tetra Methyl Ammonium Hydroxide) solution. The sensing devices with different heater materials such as metal and poly-silicon were obtained using CMOS (Complementary Metal Oxide Semiconductor) compatible process. The tellurium films as a sensing layer were deposited on the micro machined substrate using shadow silicon mask. The low power micro gas sensors showed high sensitivity to NO with high speed. The pure tellurium film used micro gas sensor showed good sensitivity than transition metal (Pt, Ti) used tellurium film.

• 센서학회지
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• 제21권5호
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• pp.389-393
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• 2012

A chaotic oscillator with light controllability was designed. The proposed chaotic oscillator consists of a photo sensor, two phase clock driven MOS switches, nonlinear function blocks for chaotic signal generation. SPICE circuit analysis using a 0.35 um CMOS process parameters was performed for its chaotic dynamics. And we confirmed that chaotic behaviors of the circuit can be controlled according to light intensity. By SPICE simulation, chaotic dynamics by time waveforms, frequency analysis was analyzed. SPICE results showed that proposed circuit can make various light-controlled chaotic signals.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.579-580
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• 2006

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.