• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1501-1502
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• 2011

In this paper, an investigation of the 8" process for Trench Power MOSFET Application and Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.353-358
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• 2007

J-shaped superluminescent diodes (SLD) utilizing trench structure have been fabricated on the multiple quantum dots epi-structure with its ground state energy wavelength of $1.3\;{\mu}m$. It was observed that optical power was drastically increased up to 20 times in comparison with that of SLD without trench structure, The electroluminescence characteristics showed that the peak intensity of excited state was several ten times higher in the SLD with trench than without trench structure. It is explained that the optical power enhancement of J-shaped SLD with trench structure resulted from the drastic increase of peak intensity of excited state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.389-389
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• 2010

In this paper, an investigation of the benefits of gate oxide for 8" the manufacturing of Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.246-246
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• 2010

As the trench width in the interconnect technology decreases down to nano-scale below 50 nm, superconformal gap-filling process of Cu becomes very critical for Cu interconnect. Obtaining superconfomral gap-filling of Cu in the nano-scale trench or via hole using MOCVD is essential to control nucleation and growth of Cu. Therefore, nucleation of Cu must be suppressed near the entrance surface of the trench while Cu layer nucleates and grows at the bottom of the trench. In this study, suppression of Cu nucleation was achieved by treating the Ru barrier metal surface with capacitively coupled hydrogen plasma. Effect of hydrogen plasma pretreatment on Cu nucleation was investigated during MOCVD on atomic-layer deposited (ALD)-Ru barrier surface. It was found that the nucleation and growth of Cu was affected by hydrogen plasma treatment condition. In particular, as the plasma pretreatment time and electrode power increased, Cu nucleation was inhibited. Experimental data suggests that hydrogen atoms from the plasma was implanted onto the Ru surface, which resulted in suppression of Cu nucleation owing to prevention of adsorption of Cu precursor molecules. Due to the hydrogen plasma treatment of the trench on Ru barrier surface, the suppression of Cu nucleation near the entrance of the trenches was achieved and then led to the superconformal gap filling of the nano-scale trenches. In the case for without hydrogen plasma treatments, however, over-grown Cu covered the whole entrance of nano-scale trenches. Detailed mechanism of nucleation suppression and resulting in nano-scale superconformal gap-filling of Cu will be discussed in detail.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.252-255
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• 2004

반도체는 high integrated, high speed, low power를 위하여 design 뿐만 아니라 재료 측면에서도 많은 변화를 가져오고 있으며, RC delay time을 줄이기 위하여 Al 배선보다 비저항이 낮은 Cu와 low-k material 적용이 그 대표적인 예이다. 그러나, Cu 배선의 경우 dry etching이 어려우므로, 기존의 공정으로는 그 한계를 가지므로 damascene 또는 dual damascene 공정이 소개, 적용되고 있다. Damascene 공정은 절연막에 photo와 RIE 공정을 이용하여 trench를 형성시킨 후 electrochemical plating 공정을 이용하여 trench에 Cu를 filling 시킨다. 이후 CMP 공정을 이용하여 절연막 위의 Cu와 barrier material을 제거함으로서 Cu 배선을 형성하게 된다. Dual damascene 공정은 trench와 via를 동시에 형성시키는 기술로 현재 대부분의 Cu 배선 공정에 적용되고 있다. Cu CMP는 기존의 metal CMP와 마찬가지로 oxidizer를 이용한 Cu film의 화학반응과 연마 입자의 기계가공이 기본 메커니즘이다. Cu CMP에서 backside pressure 영향이 uniformity에 미치는 영향을 살펴보았으며, electrochemical plating 공정에서 발생하는 hump가 CMP 결과에 미치는 영향과 dishing 결과를 통하여 그 영향을 평가하였다.

• Journal of Powder Materials
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• v.20 no.5
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• pp.355-358
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• 2013

Micro trench structures are applied in gratings, security films, wave guides, and micro fluidics. These micro trench structures have commonly been fabricated by micro electro mechanical system (MEMS) process. However, if the micro trench structures are machined using a diamond tool on large area plate, the resulting process is the most effective manufacturing method for products with high quality surfaces and outstanding optical characteristics. A nonferrous metal has been used as a workpiece; recently, and hybrid materials, including polymer materials, have been applied to mold for display fields. Thus, the machining characteristics of polymer materials should be analyzed. In this study, machining characteristics were compared between nonferrous metals and polymer materials using single crystal diamond (SCD) tools; the use of such materials is increasing in machining applications. The experiment was conducted using a square type diamond tool and a shaper machine tool with cutting depths of 2, 4, 6 and 10 ${\mu}m$ and a cutting speed of 200 mm/s. The machined surfaces, chip, and cutting force were compared through the experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.219-229
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• 2012

In the course of feasibility study the necessity of implementing electrochemical methods as an inline metrology technique to characterize semiconductor nano structures for a Deep Trench Dynamic Random Access Memory (DT-DRAM) (e.g. ultra shallow junctions USJ) was discussed. Hereby, the state of the art semiconductor technology on the advantages and disadvantages of the most recently used analytical techniques for characterization of nano electronic devices are mentioned. Various electrochemical methods, their measure relationship and correlations to physical quantities are explained. The most important issue of this paper is to prove the novel usefulness of the electrochemical micro cell in the semiconductor industry.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.2
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• pp.155-161
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• 2016

This paper proposes a novel fabrication method for a capacitive type micro-accelerometer with uniform nano-gap using photo-assisted electro-chemical etching. The sensitivity of the accelerometer should be improved while the electrodes between the inertial mass and the sensing comb should be narrowed. In this paper the nano-gap trench structure is fabricated using the photo-assisted electrochemical etching method. The sensor was designed and analysed using ANSYS simulator. The characteristics of the etching were observed according to the dc bias, the light intensity, the composition of the solution, the temperature of the solution, and the pattern pitch variation. The optimum etching conditions were dc bias of 2V, Blue LED of 20mA, 49wt% HF:DMF:D.I.Water=1:20:10, the pattern pitch of $20{\mu}m$. Uniform trench structure with width of 344nm and depth of $11.627{\mu}m$ are formed using the optimum condition.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.4
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• pp.208-211
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• 2018

This paper details the design of a 1,200 V class trench gate field stop IGBT (insulated gate bipolar transistor) with a nano gate structure smaller than 1 um. Decreasing the size is important for lowering the cost and increasing the efficiency of power devices because they are high-voltage switching devices, unlike memory devices. Therefore, in this paper, we used a 2-D device and process simulations to maintain a gate width of less than 1 um, and carried out experiments to determine design and process parameters to optimize the core electrical characteristics, such as breakdown voltage and on-state voltage drop. As a result of these experiments, we obtained a wafer resistivity of $45{\Omega}{\cdot}cm$, a drift layer depth of more than 180 um, an N+ buffer resistivity of 0.08, and an N+ buffer thickness of 0.5 um, which are important for maintaining 1,200 V class IGBTs. Specially, it is more important to optimize the resistivity of the wafer than the depth of the drift layer to maintain a high breakdown voltage for these devices.

• Proceedings of the Materials Research Society of Korea Conference
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• 2006.11a
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• pp.15.1-15.1
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• 2006