• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.240.1-240.1
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• 2013

본 연구에서는 Symmetric NMOSFET의 channel length에 따른 전기적 특성 분석에 관한 연구를 진행하였다. 특성 분석에 사용된 소자의 Gate oxide 두께는 6 nm 이며, 채널 Width/Length는 각각 10/10 ${\mu}m$, 10/0.2 ${\mu}m$ 이다. Drain Avalanche Hot Carrier(DAHC) 테스트를 진행하기 위하여 각각 스트레스 조건을 추출하였고, 조건에 해당되는 스트레스를 1700초 동안 인가하였다. 스트레스 후, Channel length가 10 ${\mu}m$과 0.2 ${\mu}m$인 두 소자의 특성을 측정, 분석결과 10 ${\mu}m$의 소자의 경우 문턱전압(VT)과 Subthreshold swing (SS)의 변화가 없었지만 0.2 ${\mu}m$의 소자의 경우 0.42V의 (from 0.67V to 1.09V) 문턱전압 변화 (VTH)와 71 mV/dec (from 79 mV/dec to 150 mV/dec))의 Swing (SS)변화를 보여 스트레스 후에 Interface trap이 증가하였음을 알 수 있다. off-state leakage current를 측정 결과 0.2 ${\mu}m$ 의 경우 leakage current의 양이 증가하였음을 알 수 있고 이는 드레인 부근에 증가된 interface trap에 의한 현상으로 판단된다. 상기 결과와 같이 DAHC 스트레스에 의한 소자의 열화 현상은 Channel length가 짧을수록 더 크게 의존하는 것을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.257-259
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• 2019

We have investigated the electrical coupling in a 3D monolithic NOR gate structure using TCAD simulation. The electrical coupling of 3D monolithic NOR gate can be caused by the transistor located in the upper/lower or diagonal transistors. The drain current of the upper layer NMOSFET is the same when the voltage of PgateB is 0 V and 1 V. It has been confirmed that the electrical coupling in the diagonal direction does not affect the device characteristics.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.29-32
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• 2002

This paper describes a novel structure of NMOSFET with elevated SiGe source/drain region and ultra-shallow source/drain extension(SDE)region. A new ultra-shallow junction formation technology. Which is based on damage-free process for rcplacing of low energy ion implantation, is realized using ultra-high vacuum chemical vapor deposition(UHVCVD) and excimer laser annealing(ELA).

• Journal of Sensor Science and Technology
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• v.21 no.6
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• pp.413-419
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• 2012

A dynamic range extension technique is proposed based on a 3-transistor active pixel sensor (APS) with gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector using a feedback structure. The new APS consists of a pseudo 3-transistor APS and an additional gate/body-tied PMOSFET-type photodetector, and to extend the dynamic range, an NMOSFET switch is proposed. An additional detector and an NMOSFET switch are integrated into the APS to provide negative feedback. The proposed APS and pseudo 3-transistor APS were designed and fabricated using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) process. Afterwards, their optical responses were measured and characterized. Although the proposed pixel size increased in comparison with the pseudo 3-transistor APS, the proposed pixel had a significantly extended dynamic range of 98 dB compared to a pseudo 3-transistor APS, which had a dynamic range of 28 dB. We present a proposed pixel that can be switched between two operating modes depending on the transfer gate voltage. The proposed pixel can be switched between two operating modes depending on the transfer gate voltage: normal mode and WDR mode. We also present an imaging system using the proposed APS.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.46-51
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• 1989

The degradation phenomena induced by hot-carrier injection was studied from the shift of threshold voltage and subthreshold current curve in LDD NMOSFET degraded under different DC stress-biases. Threshold voltage shift ${Delta}V_{tex}$ defined in saturation region was separated into contri butions due to trapped oxide charge $V_{ot}$ and interface traps ${Delta}V_{it}$ generated from midgap to threshold voltage. Under th positive stress electric field (TEX>$V_g>V_d$) condition, the shift of threshold voltage was attributed to the electrons traped ar gate oxide but subthreshold swing was not negative stress electric field ($V_g) condition, holes seems to be injected positive charges so threshold voltage and subthreshold swing were increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.24-29
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• 2009

In order to model the high temperature dependence of the cutoff frequency $f_T$ in $0.18{\mu}m$ deep n-well isolated bulk NMOSFET, high temperature data of electron velocity of bulk MOSFETs from $30^{\circ}C$ to $250^{\circ}C$ are obtained by an accurate RF extraction method using measured S-parameters. From these data, an improved temperature-dependent electron velocity equation is developed and implemented in a BSIM3v3 SPICE model to eliminate modeling error of a conventional one in the high temperature range. Better agreement with measured $f_T$ data from $30^{\circ}C$ to $250^{\circ}C$ are achieved by using the SPICE model with the improved equation rather than the conventional one, verifying its accuracy of the improved one.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.6
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• pp.424-429
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• 1987

It has been observed that the reduction rate of the inversion layer carrier mobility due to the increase of the longitudinal electric field(drain to source direction) decreases as the transverse electric field increases. The effects of this physicar phenomenon to the I-V characteristics of the short channel NMOSFET are studied. It is shown that these effects increase the drain Current in the saturatio region, which agrees with the genarally observed decrepancy between the experimental I-V charateristics and the I-V modeling which dose not include this physical phenomenon. Also it is shown that this effect becomes more important when the device channel length decreases and the device operates in the high electric field range.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• Journal of IKEEE
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• v.21 no.2
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• pp.150-153
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• 2017

In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.