• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.569-571
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• 1995

This paper compares the simulated annealing and the Hopfield neural network method for an optimal routing in a multistage interconnection network(MIN). The MIN provides a multiple number of paths for ATM cells to avoid cell conflict. Exhaustive search always finds the optimal path, but with heavy computation. Although greedy method sets up a path quickly, the path found need not be optimal. The simulated annealing can find an sub optimal path in time comparable with the greedy method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6B
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• pp.563-574
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• 2004

In this paper, we propose a new class of MIN(Multistage Interconnection Network) called Combine MIN which combines static network topology and apimic network topology. Combine U provides multiple paths at a hardware cost lower than that of MIN with unique path property. Combine MIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. According to the results of analysis and simulation for performance evaluation, Combine MIN shows higher performance than MINs of the same network size in the highly localized communication Therefore, Combine MIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.738-748
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• 2002

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches is Proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered${\alpha}{\times}{\alpha}$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes, Two important parameters of the network performance, throughput and delay, are then evaluated, To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.149-159
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• 2000

In this paper, we propose a new class of MIN (Multistage Interconnection Network) called SCMIN(ShortCut MIN) which can form a cheap and efficient packet switching interconnection network. SCMIN satisfies full access capability(FAC) and has multiple redundant paths between processor-memory pairs even though SCMIN is constructed with 2.5N-4 SEs which is far fewer SEs than that of MINs. SCMIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. Therefore, SCMIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.6
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• pp.675-685
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• 1989

The interconnection network is an integral part of parallel processing system. The multistage interconnection networks(MINs) have been the objects of intense research in recent years. In this paper, simulation techniques for circuit switchign MIN are extended to allow the performance evaluation of partitioned ADM/IADM network. Based on simulation data, the relationship between the netwrok performance, the partitioning scheme employed, and the conflict resolution strategies used within the network is enumerated. It is shown that IADM network coupled with the use of the hold strategy produces the best network operation in terms of RST (Request Service Time).

• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.35-43
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• 2004

In packet switching using multistage interconnection networks (MIN's), it is generally assumed that the packet movements successively propagate from the last stage to the first stage in one network cycle. However, Ding and Bhuyan has shown that the network performance can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this paper, an analytical model for evaluating the performance of input-buffered MlN's employing this network cycle approach is proposed, The effectiveness of the proposed model is confirmed by comparing results from the simulation as well as from Ding and Bhuyan model.

• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2259-2268
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• 1997

Multistage interconnection networks(MINs) provide a high-bandwidth communication between processors and/or memory modules in a cost-effective way. In this paper, we propose a class of multipath MINs, called the Augmented Modified Delta(AMD) network, and analyze its performance and reliability. The salient features of the AMD network include fault-tolerant capability, modular structure, and high performance, which are essential for real-time parallel/distributed processing environments. The class of the AMD network retains well-known characteristics of the Kappa network, but it's design procedure is more systematic. Like Delta networks, all the AMD networks are topologically equivalent with each other.

• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.199-202
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• 2001

In this paper, we proposed and analyzed a new class of irregular fault-tolerant multistage interconnection network named as Extended-QT(Quad Tree) network. E-QT network is extended QT network. A unique path MIN usually is low hardware complexity and control algorithm. So we proposes a class of multipath MIN which are obtained by adding self-loop auxiliary links at the a1l stages in QT(Quad Tree) networks so that they can provide more paths between each source-destination pair. The routing of proposed structure is adaptived and is based by a routing tag. Starting with the routing tag for the minimum path between a given source-destination pair, routing algorithm uses a set of rules to select switches and modify routing tag. Trying the self-loop auxiliary link when both of the output links are unavailable. If the trying is failure, the packet discard. In simulation, an index of performance called reliability and cost are introduced to compare different kinds of MINs. As a result, the prouosed MINs have better capacity than 07 networks.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.3
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• pp.117-124
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• 2002

This paper proposes a fault-tolerant multicasting algorithm employing the region encoding scheme in multistage interconnection networks (MIN's) containing multiple faulty switching elements. After classifying all switching elements into two subsets with equal sizes in MIN, the proposed algorithm can tolerate the faulty pattern where every fault is contained in the same subset. In order to send a multicast message to its destinations detouring faults, the proposed algorithm uses the recursive scheme that recirculates it through MIN, We prove that this algorithm can route any multicast message in only two passes through the faulty MIN.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.193-202
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• 2007

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.