Journal of KIISE:Information Networking (한국정보과학회논문지:정보통신)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지

Performance Evaluation for a Multistage Interconnection Network with Buffered $a{\times}a$ Switches under Hot-spot Environment

핫스팟을 발생시 출력 버퍼형 $a{\times}a$ 스위치로 구성된 다단 연결망의 성능분석

  • 김정윤 (울산대학교 전기전자정보시스템공학부) ;
  • 신태지 (울산대학교 전기전자정보시스템공학부) ;
  • 양명국 (울산대학교 전기전자정보시스템공학부)
  • Published : 2007.06.15
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

본 논문에서는, $a{\times}a$ 출력 버퍼 스위치로 구성되며 핫스팟이 발생하는 다단 연결 망 (Multistage Interconnection Network， MIN)의 성능 예측 모형을 제안하고, 스위치에 장착된 버퍼의 개수 증가에 따른 성능 향상 추이를 분석하였다. 제안한 성능 예측 모형은 먼저 네트워크 내부의 임의 스위치 입력 단에 유입되는 데이타 패킷이 스위치 내부에서 전송되는 유형을 확률적으로 분석하여 수립되었다. 성능분석 모형은 스위치에 장착된 버퍼의 개수와 무관하게 버퍼를 장착한 $a{\times}a$ 스위치의 성능, 네트워크 정상상태 처리율(Normalized Throughput, NT)과 네트워크 지연시간(Network Delay)의 예측이 가능하고, 나아가서 이들로 구성된 모든 종류의 다단 연결망 성능 분석에 적용이 용이하다. 제안한 수학적 성능 분석 연구의 실효성 검증을 위하여 병행된 시abf레이션 결과는 상호 미세한 오차 범위 내에서 모형의 예측 데이타와 일치하는 결과를 보여 분석 모형의 타당성을 입증하였다.

Keywords

References

  1. S. H. Byun, D. K. Sung, 'The UniMIN Swithch Architecture for Large-Scale ATM Switches,' IEEE Trans. on Networking, Vol.8, No.1, pp.109-120, Feb. 2000 https://doi.org/10.1109/90.836482
  2. G. F. Pfister, W. C. Brantley, et al., 'The IBM Research Parallel processor Prototype(RP3): Introduction and Architecture,' Proc. Intl. Conf.om Parallel Processing, pp.764-771, Aug. 1985
  3. D. M. Dias and J. R. Jump, 'Analysis and Simulation of Buffered Delta Networks,' IEEE Trans. on Computers, Vol.C-30, No.4. pp.273-282, Apr. 1981 https://doi.org/10.1109/TC.1981.1675775
  4. Y. C. Jenq, 'Performance Analysis of a Packet Switch Based on Single Buffered Banyan Network,' IEEE J. Select. Areas Comm., Vol. SAC-3, No.6, pp.1014-1021, Dec. 1983 https://doi.org/10.1109/JSAC.1983.1146023
  5. C. P. Krusal and M. Snir, 'The Performance of Multistage Interconnection Networks for Multiprocessors,' IEEE Trans. on Computers, Vol.C-32, No.12. pp.1091-1098, Dec. 1983 https://doi.org/10.1109/TC.1983.1676169
  6. H. Yoon, K. T. Lee, and M. T. Liu, 'Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems,' IEEE Trans. on Computers, Vol.C-39, No.3, pp.319-327, Mar. 1990 https://doi.org/10.1109/12.48863
  7. Y. Mun and H. Y. Youn, 'Performance Analysis of Finite Buffered Multistage Interconnection Networks,' IEEE Trans, on Computers, Vol.43, No.2, pp.153-162, Feb. 1994 https://doi.org/10.1109/12.262120
  8. Chita R. Das and Prasant Mohapatra, 'Performance Analysis of Finite-Buffered Asynchronous Multistage Interconnection Networks,' IEEE Trans. on Parallel and Distributed systems, Vol.7, No.1, pp. 18-25, Jun 1996 https://doi.org/10.1109/71.481594
  9. Mahmoud Saleh and Mohammed Atiquzzaman, 'Analysis of Shared Buffer Multistage Networks with Hot Spot,' IEEE First International Conference on Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95 https://doi.org/10.1109/ICAPP.1995.472270
  10. Chuan-Lin Wu and Tse-Yun Feng, 'On a class of Multistage Interconnection Networks,' IEEE Trans. on Computers, Vol.C-29, No.8, pp.108-116, Aug. 1980 https://doi.org/10.1109/TC.1980.1675651
  11. Myung K Yang and Tae Z Shin, 'Performance Evaluation of the Buffered MIN with $a{\times}a$ Switches,' KISS Conf. on Parallel Processing, pp.244-246, Nov. 2000
  12. G.F. Pfister and V.A. Norton, 'Hot spot contention and combining in multistage interconnection networks,' IEEE Trans. on Computers, Vol.C34, No.10, pp.943-948, October 1985
  13. Tae Z. Shin, Jun Lee and Myung K. Yang, 'Evaluation of a Fat-tree Network with Buffered $a{\times}b$ Switches,' IEEE Conf. PACRIM'03, pp.205- 208, Aug. 2003
  14. Tae Z. Shin and Myung K. Tang, 'Performance Evaluation of a Switch Router with Output - Buffer,' KISS Trans. Vol.32, No.2, pp.244-253, Apr, 2005