• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.968-972
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• 2009

The multi-core processors are being widely exploited by many high-end systems. With significant advances in processor architecture, the network band-width required on the high-end systems is increasing drastically. It is therefore highly desirable to manage multiple cores efficiently to achieve high network band-width with minimum resource requirements. Modern operating systems, however, still have significant design and optimization space to leverage the network performance over multi-core systems. In this paper, we suggest a novel networking process scheduling scheme, which decides the best processor affinity of networking processes based on the processor cache layout, communication intensiveness, and processor loads. The experimental results show that the scheduling scheme implemented in the Linux kernel can improve the network bandwidth and the effectiveness of processor utilization by 20% and 59%, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.270-273
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• 2012

In this paper, I present the design of Operational Flight Programs(OFPs) on a Multi-Core based Mission Computer(MC) for the optimized performance of the OFPs on Multi-Core based MC. The program assigned as tasks on Multi-Core environment can be scheduled by designing with the use of OpenMp, which is the standard for parallel programming. This paper also describes the differences between Multi-Core Program(MCP) on the technique and Single-Core Program(SCP) in terms of performance aspect. The new proposed design technique is applied to the Integrated Up-Front Control OFP(IUFC OFP) on General Processor Module where Multi-Core based. This paper describes the Multi-Core design technique for the optimized performance of the IUFC OFP, which display and control flight data(Navigation, Communication, Identification Friend or Foe) to pilot.

• The Journal of the Korea Contents Association
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• v.12 no.6
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• pp.68-77
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• 2012

As the system development environment moves from single core to multi core-based platforms, it becomes more important to maintain compatibility between single core-based implementations and multi core-based implementations. Moreover, it is very important to support real-time on multi core platforms especially in cases of embedded software or test equipments which need real-time as well as correctness. Since Windows operating system dopes not support real-time in itself, it has been supporting real-time using expensive third-party solutions such as RTX or INtime. So as to reduce this kind of development expenses, in this paper, we propose RTiK-MP(Real-Time implant Kernel-Multi Processor) which supports real-time on Windows using the Local APIC of x86 architectures, and evaluate the performance of the proposed RTiK-MP after deploying it on portable missile test equipments.

• Transactions of the Korean Society of Automotive Engineers
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• v.24 no.2
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• pp.127-136
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• 2016

The camera based object detection systems should satisfy the recognition performance as well as real-time constraints. Particularly, in safety-critical systems such as Autonomous Emergency Braking (AEB), the real-time constraints significantly affects the system performance. Recently, multi-core processors and system-on-chip technologies are widely used to accelerate the object detection algorithm by distributing computational loads. However, due to the advanced hardware, the complexity of system architecture is increased even though additional hardwares improve the real-time performance. The increased complexity also cause difficulty in migration of existing algorithms and development of new algorithms. In this paper, to improve real-time performance and design complexity, a task scheduling strategy is proposed for visual object tracking systems. The real-time performance of the vision algorithm is increased by applying pipelining to task scheduling in a multi-core processor. Finally, the proposed task scheduling algorithm is applied to crosswalk detection and tracking system to prove the effectiveness of the proposed strategy.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.2
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• pp.131-136
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• 2013

Multi-core processors can improve parallelism of application processes and thus can enhance the system throughput. Researchers have recently revealed that the processor affinity is an important factor to determine network I/O performance due to architectural characteristics of multi-core processors; thus, many researchers are trying to suggest a scheme to decide an optimal processor affinity. Existing schemes to dynamically decide the processor affinity are able to transparently adapt for system changes, such as modifications of application and upgrades of hardware, but these have limited access to characteristics of application behavior and run-time information that can be collected heuristically. Thus, these can provide only sub-optimal processor affinity. In this paper, we define meaningful system variables for determining optimal processor affinity and suggest a tool to gather such information. We show that the implemented tool can overcome limitations of existing schemes and can improve network bandwidth.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.1-10
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• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.1
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• pp.163-169
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• 2013

Recently, the importance of embedded system is growing rapidly. In-order to satisfy the real-time constraints of the system, high performance embedded processor is required. Therefore, as in general purpose computer systems, embedded processor should be designed as multicore architecture as well. Using MiBench benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2-core to 16-core embedded processor architectures with different types of cores from simple RISC to in-order and out-of-order superscalar processors, extensively. As a result, the achievable performance is as high as 23 times over the single core embedded RISC processor.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.99-104
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• 2013

Recently smart devices which combine traditional electronic devices and personal computers, such as smart phones and smart TV, have caught people's eyes from all over the world. A multi-media SoC platform which embeds not only a calculating processor but also an operating system could provide an user-customized environment of several types of communication methods to PC or Internet. In this paper, we describe a multi-functioning SoC platform with video, audio and other communicating protocols based on Core-A processor and AMBA buses. To verify the designed multi-media SoC platform, JPEG decoding and ADPCM encoding/decoding algorithms are applied on it and the final decoding results are confirmed by video monitors and audio speakers.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.131-140
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• 2011

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.