• Korean Journal of Optics and Photonics
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• v.17 no.3
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• pp.278-284
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• 2006

We have fabricated and measured electrooptic modulator using coupled stack InAs/InGaAs quantum dots. The height of the quantum dot is 16 nm and quantum dots are stacked including an InGaAs capping layer. The peak wavelength of photoluminescence is 1260 nm at room temperature and 1158 nm at 12 K. The operation characteristics of the quantum dots show high modulation efficiency of electrooptic modulator at 1550 nm compared to that of existing III-V bulk and MQW type semiconductor. The measured switching voltage ($V\pi$) is 540 and 600 mV, for TE mode and TM mode, respectively. From the results, the modulation efficiency can be determined as 333.3 and $300^{\circ}/V{\cdot}mm$ for TE and TM modes. The results reported here may lead to the design and fabrication of a novel electrooptic modulator with low switching voltage and high efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.6
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• pp.435-443
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• 2017

In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.103-110
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• 2010

In this paper, a new mode changeable asymmetric full bridge dc/dc converter is proposed to solve the freewheeling current problem of the conventional zero voltage switching(ZVS) phase shift full bridge(PSFB) dc/dc converter of low output voltage and high output current applications. The proposed converter is operated as an asymmetric full bridge converter when the duty cycle is less than 50% and active clamp full bridge converter when the duty cycle is greater than 50%. As a result, since its freewheeling current is eliminated, the conduction loss is lower than that of the conventional ZVS PSFB dc/dc converter. Moreover, ZVS of all power switches can be ensured along a wide load ranges and output current ripple is very small. Therefore, high efficiency of the proposed converter can be achieved. Especially since its operation mode is changed to the active clamp full bridge converter during hold up time and can be operated with 50~100% duty ratio, it can produce the stable output voltage along wide input voltage range. The operational principles, theoretical analysis and design considerations are presented. To confirm the operation, validity and features of the proposed converter, experimental results from a 1.2kW($400V_{dc}/12V_{dc}$) prototype are presented.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.

• Korean Journal of Optics and Photonics
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• v.14 no.5
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• pp.545-554
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• 2003

Design of the optical modulator composed of a three-waveguide coupler and CPW traveling-wave electrodes was carried out. Switching phenomena of three-waveguide couplers were analyzed by using the coupled mode theory, and the coupling-lengths of the devices were calculated by means of the FDM. CPW traveling-wave electrodes were analysed by the CMM and SOR simulation technique in order to find the conditions of phase-velocity and impedance matching. Traveling-wave modulators were fabricated on z-cut LiNbO$_3$ substrate. Ti was in-diffused in LiNbO$_3$ to make waveguides and Au electrodes were built on the waveguides by the electrolyte technique. The fabricated modulator chip was end-polished, pig-tailed and packaged in a brass mount with K-connector. The insertion loss and the switching voltage of the optical modulator were about 4㏈ and 19V, respectively. Network analyzer was used to obtain the S parameter and the corresponding RF response. From the measurement, parameters of the traveling-wave electrodes were extracted to be Z$_{c}$= 45 Ω, N$_{eff}$=2.20, and $\alpha$$_{0}$=0.055/cm√GHZ. The measured optical response R($\omega$) was compared with the theoretically estimated one, showing both responses agree well. The measurement results revealed that 3㏈ bandwidth turned out to be about 13 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.183-190
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• 2010

We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.91-102
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• 1996

The multicast routing algorithm is necessary to transmit multimedia traffic efficiently in ATM (asynchronous transfer mode) networks. In this paper, we propose the multicast routing algorithm which is based on VP/VC characteristic. The proposed algorithm is based on VP tree concept and using cost function which is based on VP/VC switching. The cost funication is composed of link cost, delay and weighting factor on delay and the weighting factor is calculated by delay sensitivity of the traffic. The proposed algorithm can choose delay bounded path which satisfies delay constraint, moreover it can choose optimal path among VPs which has the same link cost and satisfying delay constraint. With controlling weighting factor, proposed algorithm can set-up efficient path. When the weighting factor sets to be between 0.8 and 1, experimental results show that the perforance of proposed scheme is approximated to that of cost optimal algorithm and strongly delay optimized algorithm.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.843-846
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• 2004

For the fast growing Liquid Crystal Display (LCD) TV market, it is essential to make the LCD panels to show moving images without any visual difficulties such as blurring or tailing. Owing to reduction of the cell gap and the improved Liquid Crystal (LC) mixtures with low viscosity, it is possible that our S-IPS TFT-LCDs feature a response time (R/T) as fast as 1-frame time (16ms) for a white-black operation and less than a 16rns in all gray levels without Over Driving Circuit (ODC) technology. Currently, mass production of the large size IPS panels with high speed has been successfully achieved. In order to achieve faster response time, new LC mixtures have been developed, optimizing the physical properties of rotational viscosity (${\gamma}$1) and elastic constants (Kii). Also, the LC mixtures with high elastic constant allow us to increase the cell gap. In this paper, realization of fast switching time in IPS mode with optimized '${\gamma}$1/Kii' parameter in the LC mixtures forms the core of this paper.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.5
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• pp.96-104
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• 2004

This paper proposes a dc power regenerating systems, which can generate the excessive dc power from dc bus line to ac supply in substations for traction system The proposed regeneration inverter system for dc traction can be used as both an inverter and an active power filter(APF). As an regeneration inverter mode, it can recycle regenerative energy caused by decelerating tractions and as an active power filter mode, it can compensate for harmonic distortion produced by the rectifier substation. From the viewpoint of both power capacity and switching losses, the system is designed on the basis of three phase PWM inverters and composed of parallel inverters, output transformers, and an LCL filter.