• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of information and communication convergence engineering
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• v.9 no.4
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.70-75
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• 2016

This paper proposes the constructing method of effective multiplier based on the finite fields in case of P=2. The proposed multiplier is constructed by polynomial arithmetic part, mod F(${\alpha}$) part and modular arithmetic part. Also, each arithmetic parts can extend according to m because of it have modular structure, and it is adopted VLSI because of use AND gate and XOR gate only. The proposed multiplier is more compact, regularity, normalization and extensibility compare with earlier multiplier. Also, it is able to apply several fields in recent hot issue IoT configuration.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.3 no.1
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• pp.18-30
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• 1985

This paper describes a logical design of ternary arithmetic circuits based on T-gates. A new circuit of T-gate is proposed which is improved in the stability of operation, and a ternary adder, subtracter, multiplier and divider using the T-gates are realized. The realization of the circuits is based on the Mod-3, system and the Signed Ternary system using digit 0, 1, 2 and -1, 0, +1 as arithmetic states.

• Research in Mathematical Education
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• v.8 no.3
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• pp.215-226
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• 2004

The purpose of this paper is to introduce an activity of student who found purely linear algebraic solution of the Blackout puzzle. It shows how we can help and work with gifted students. It deals with algorithm, mathematical modeling, optimal solution and software.

• Communications of Mathematical Education
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• v.21 no.4
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• pp.597-612
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• 2007

For finding the optimal strategy in Blackout game which was introduced in the homepage of popular movie "Beautiful mind", we have developed and generalized a mathematical proof and an algorithm with a couple of softwares. It did require only the concept of basis and knowledge of basic linear algebra. Mathematical modeling and analysis were given for the square matrix case in(Lee,2004) and we now generalize it to a generalized $m{\times}n$ Blackout game. New proof and algorithm will be given with a visualization.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.318-321
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• 2000

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.281-286
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• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.