• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.1
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• pp.82-89
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• 2014

Recently, inertial sensors are popularly used for the location and position recognition of small devices for M2M/IoT. In this paper, we designed low power, low noise, small sized 6-axis inertial sensor IC for mobile applications, which uses a 3-axis piezo-electric gyroscope sensor and a 3-axis piezo-resistive accelerometer sensor. Proposed IC is composed of 3-axis gyroscope readout circuit, two gyroscope sensor driving circuits, 3-axis accelerometer readout circuit, 16bit sigma-delta ADC, digital filter and control circuit and memory. TSMC $0.18{\mu}m$ mixed signal CMOS process was used. Proposed IC reduces 27% of the current consumption of LSM330.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.847-850
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• 1998

One of the most difficult problem of designing VLSI is a mixed-circuit design, that is to design circuit containing both analog parts and digital parts. Digital to analog converter and analog to digital converter is a typical case. Especially it can be a serious problem when mixed circuit are put into a large digital circuit like microcontroller. However nowadays this problem is settled by separating analog circuit parts outside the IC. This technique is based on converting a digital signal into a pulse sequence. Then an analog signal is obtained by averaging this pulse sequence at the external low-pass filter. An anlog to digital converter is designed using a stochastic logic instead of a traditional PWM (pulse-width modulation) signal and ins implemente dusing FPGa. Stochastic pulse sequence can be made as a simple circuits and moreover can be mathematically processed by simple circuits -AND gates. The spectral property of stochastic pulse sequence method is better than that of PWM method. So it make easy to design a external low-pass filter. This technique has important advantages, especially the reduction of the ADC cost.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.278-285
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• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1862-1863
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• 2007

Testing the analog/mixed-signal circuitry of a mixed-signal IC has become a difficult task. Offset error, gain error, Non-monotonic behavior, Differential Non-linearity(DNL) error, Integral Non-linearity(INL) error are important specifications used as test parameters for DAC. In this paper, we propose an efficient BIST structure for DAC testing. The proposed BIST adds the circuit which uses the capacitor and op-amp, and accomplishes a test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.375-379
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• 2016

A current subtraction technique with parallel operation system is proposed to remove excessive current in touch screen application. The proposed current subtraction remove the current which go into the input node of charge amplifier. The value of subtraction current is same with current when touch screen is not touched. As a result, charge amplifier output is only proportional to variation of mutual capacitor, which make dynamic rage is increased. Also, Transmitter (Tx) driving signal and subtraction driving signal are out of phase each other. Thus, noise generated in Tx is cancelled. The proposed IC is implemented in a mixed-mode 0.18-um CMOS process. Overall system is designed for touch screen panel (TSP) with 16 driving lines and 8 sensing lines. 5-V supply voltages are used in the proposed circuits. For multiple Tx driving signal, Walsh codes are used and signal frequency is 300 khz. By using proposed technique, dynamic rage is improved 36 dB.

• The Magazine of the IEIE
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• v.42 no.7
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• pp.45-53
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• 2015

Power 소자 기술은 digital & mixed signal device와 on-chip 구현을 위해서 CMOS 공정에 대한 기본 이해가 필요하다. CMOS 공정 기반 위에 power device 공정을 추가하면서 다양한 operation voltage의 power 소자를 구현하고, passive device 들을 동일 공정에서 구현하여 다양한 components 들로 power IC 제품을 design 할 수 있도록 modular process를 제공하는 것이 중요하다. 또한 power device로 주로 사용되는 LDMOS 소자에 대한 performance 개선을 위해 simulation을 통해 key device parameter들의 특성을 예측하고, 구조를 설계하는 것이 Si process 전에 중요한 일 중의 하나이다. 아울러 power management가 potable power, consumer electronics 및 green energy에서 가장 빠르게 성장하는 분야이므로, 차별화된 power 소자 기술을 확보하여 급변하는 시장 환경에 대응하는 것이 필요하다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.523-526
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• 2001

In this paper, we design and fabricate the high-efficiency and low-power switched-capacitor DC-DC converter. This converter consists of internal oscillator, output driver and output switches. The internal oscillator has 100kHz oscillation frequency and the output switches composed of one pMOS transistor and three nMOS transistors. According to the configuration of two external capacitors, the converter has three functions that are the Inverter, Doubler and Divider. The proposed converter is fabricated through the 0.8$\mu\textrm{m}$ 2-poly, 2-metal CMOS process. The simulation and experimental result for fabricated IC show that the proposed converter has the voltage conversion efficiency of 98% and power efficiency more than 95%.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.239-242
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• 2003

Optical module package is a hermetic metal-ceramic package for carrying optical IC. In case of LD(laser diode) module, window is used for both the path of optical signal and hermetic sealing of package. So, window has the metallization pattern on the surface for brazing process with package wall. In this study, several method were investigated for metallization. Thin film, thick film and mixed method were used for fabrication of metallization pattern. After brazing process, hermeticity and adhesion strength were tested for characterization of metallization pattern.