• Journal of Information Display
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• v.2 no.2
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• pp.39-44
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• 2001

The conditions of the wall charges and priming particles in a unit discharge cell in AC PDP seriously affect the addressing discharge characteristics in the driving method with ramped setup pulse. Moreover, the discharge conditions at the end of the scan line may be different from the first scan line because of the difference of about 1ms address time. Consequently, the addressing time and its dispersion may be different for any two discharge cells that lead to misfiring and the increase in the total addressing time. In order to improve the addressing time and its dispersion, we have applied different addressing voltage at each cell such as progressively increase pulse voltage instead of constant one. As a result, the addressing time and its dispersion of all cells were improved by about 30% compared with the conventional driving method.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2156-2159
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• 2005

ADS(Address Display Period Separation) driving method has been considered to be the most appropriate driving technique for AC PDP. ADS driving method is composed of reset, address, sustain and erase period. Therefore, a long time should be allocated to an address period, which results in a reduction of brightness. To realize a high luminance and high picture quality, it is necessary to high speed addressing. However, address discharge time lag increases as the temperature decreases, which can cause the misfiring and low picture quality In this paper, the electric field effect and priming particle effect are investigated in order to reduce the address discharge time lag at low temperature. Address discharge time lag was reduced effectively when the priming particles are provided.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.726-729
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• 2003

A new driving method is proposed to reduce the address period. The scan time of new driving method overlaps with the next scan time during the discharge lag time. Thus, without reducing the address pulse width and the scan pulse width, the new addressing method can reduce the address period. The results show that the scan time of about 100ns ${\sim}$ 300ns can be overlapped without the misfiring,.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.3
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• pp.1-8
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• 2013

Plasma display panel (PDP) televisions are facing to have a new chance to receive attention along with a boom in 3-D software and contents because PDP can provide the comfortable and realistic 3-D images. The PDP has three driving circuit boards such as X, Y and addressing boards. Cost effective driving waveform has already been reported to decrease the number of driving circuit board. Half bridge based sustaining driver can remove a sustaining driver in the X board. However, the biasing circuit in the X driving boards cannot be reduced because there are some drawbacks such as unstable gas discharge condition and unreliability of an address driver IC. In this paper, the half bridge based sustaining driver is considered and a simple address driver is proposed to remove one driving board, X driving board. The stable gas discharge condition, reliability of the address driver IC and the low cost can be obtained by the proposed circuit.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1151-1156
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• 2009

Unstable sustain discharges can occur at the bottom cells of the panel at high temperature. To solve this problem, the wall charge variation during an address period was investigated. A test panel of 7.5 inch XGA level was used and one green cell was measured. In order to realize operating condition equal to that of the bottom cells of 50 inch panel, the addressing stress pulses are applied. It seems that the resultant wall charge loss during address period increased with increase of stress time, temperature, pressure and Xe %. Wall charge loss increases with potential difference between scan electrode and address electrode, therefore wall charge loss can be minimized by the increase of scan voltage during address period.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.165-167
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• 2002

Stable reset and address discharge are very important when they show apparent display. But the shape of reset and address discharge and wall-charge distribution change, according to the variation on temperature. Namely, it is very difficult to show exact picture. This study represents how Dynamic Margin is height and dielectric thickness. When barrier rib height is $100{\mu}m$ and dielectirc thickness is $40{\mu}m$, it is responded the most sensitively by decreasing temperature.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.13-18
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• 2005

The variation of discharge characteristics of an ac PDP was observed with the charge of scan electrode driving circuit. Conventional scan electrode driving circuit provides two switches per one scan line, and the suggested one can be constituted by one switch per one scan line with the consideration of capacitive load characteristic of an ac PDP. To verify the workability of the suggested scheme, the performances of the ac PDP was investigated. The dynamic voltage margin was slightly decreased with the adoption of the suggested scheme, which is estimated to result from the misfiring of unselected discharge cells due to the deformation of voltage level of the neighboring scan electrode. In the observation of the delay characteristics of addressing discharge, the performances of the conventional circuit and the suggested one are assumed to be equivalent.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.329-332
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• 2003

The effects of an auxiliary address pulse driving scheme, in which an auxiliary short pulse was applied to the address electrode during a sustain-period, was examined under the various image patterns of the 42-inch WVGA ac-PDP. When the auxiliary address pulse driving scheme was applied, the luminance of the red, green and blue cells were measured respectively. The luminance, luminous efficiency and current were measured under the full-white pattern of the 42-inch ac-PDP. As a result, the luminance of blue cell was improved approximately by 17 %, whereas the luminous efficiency of the full-white pattern was improved approximately by 34 % without a misfiring discharge in comparison with conventional driving scheme.

• Journal of Information Display
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• v.5 no.1
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• pp.16-21
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• 2004

The effects of an auxiliary address pulse driving scheme, in which an auxiliary short pulse is applied to the address electrode during a sustain-period, were examined under the various image patterns of the 42-inch WVGA ac-PDP. When the auxiliary address pulse driving scheme was applied, the luminance of the red, green and blue cells were measured respectively. And the luminance, luminous efficiency, and current were measured under the full-white pattern of the 42-inch ac-PDP. As a result, the luminance of blue cells was improved approximately by 17 %, whereas the luminous efficiency of the full-white pattern was improved approximately by 34 % without a misfiring discharge in comparison with conventional driving scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.135-139
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• 2015

The address discharge time lags are investigated in each subfield time in AC plasma display panel and a modified driving waveform is proposed to reduce the address discharge time lag by applying different additional scan voltage under no misfiring discharge production. The weak plasma discharge in AC PDP is generated by applying high positive-going ramp waveform to the scan electrode during the first reset period and that induce the production of the priming particle and wall charge. Because the wall charge becomes the wall voltage in a cell, the wall plus external address voltage produce the address discharge. However, as the wall charge in a cell is gradually disappeared as time passed, the address discharge time in the subfield time for 1 TV frame is lagged. In the first subfield time, the address discharge is faster produced than the other subfield time because the wall charge are much remained by the high positive-going ramp voltage during the reset period in the first subfield time. Meanwhile, from the second to last subfield, the address discharge production time is gradually delayed due to the dissipation of the wall charge in a cell. In this study, the address discharge time lags are measured in each subfield time and the total address discharge time lags are shortened by applying the different additional scan voltage during the address period in each the subfield time.