• Title/Summary/Keyword: Micro-electronics

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A Study on the Micro-defects Characteristics and Latch-up Immune Structure by RTA in 1MeV P Ion Implantation (1MeV 인 이온 주입시 RTA에 의한 미세결함 특성과 latch-up 면역에 관한 구조 연구)

  • Roh, Byeong-Gyu;Yoon, Seok-Beom
    • Journal of IKEEE
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    • v.2 no.1 s.2
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    • pp.101-107
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    • 1998
  • This paper is studied micro-defect characteristics by phosphorus 1MeV ion implantation and Rs, SRP, SIMS, XTEM for the RTA process was measured and simulated. As the dose is higher, the Rs is lower. When the dose are $1{\times}10^{13}/cm^2,\;5{\times}10^{13}/cm^2,\;1{\times}10^{14}/cm^2$, the Rp are $1.15{\mu}m,\;1.15{\mu},\;1.10{\mu}m$ respectively. As the RTA time is longer, the maximum concentration position is deeper from the surface and the concentration is lower. Before the RTA was done, we didn't observe any defect. But after the RTA process was done, we could observe the RTA process changed the micro-defects into the secondary defects. The simulation using the buried layer and connecting layer structure was performed. As results, the connecting layer had more effect than the buried layer to latch-up immune. Trigger current was more $0.6mA/{\mu}m$ and trigger voltage was 6V at dose $1{\times}10^{14}/cm^2$ and the energy 500KeV of connecting layer Lower connecting layer dose, latch-up immune characteristics was better.

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Thermal Compression of Copper-to-Copper Direct Bonding by Copper films Electrodeposited at Low Temperature and High Current Density (저온 및 고전류밀도 조건에서 전기도금된 구리 박막 간의 열-압착 직접 접합)

  • Lee, Chae-Rin;Lee, Jin-Hyeon;Park, Gi-Mun;Yu, Bong-Yeong
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2018.06a
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    • pp.102-102
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    • 2018
  • Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

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Optimization of Optical Structure of Lightguide Panel for Uniformity Improvement of Edge-lit Backlight (엣지형 LED 백라이트의 균일도 향상을 위한 도광판의 광구조 최적화)

  • Lee, Jung-Ho;Nahm, Kie-Bong;Ko, Jae-Hyeon;Kim, Joong-Hyun
    • Korean Journal of Optics and Photonics
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    • v.21 no.2
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    • pp.61-68
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    • 2010
  • Optical simulation methods were applied to the edge-lit LED backlight for LCD TV applications in order to optimize the optical structure of the light guide plate(LGP), and thus to improve the uniformity properties by removing the bright spots caused by LED's. The edge-lit LED backlight consisted of three white LED's with a lamp cover, a light guide plate, and a reflection film. When there was no pattern on the entrance side surface of the LGP, the illuminance uniformity was sensitively dependent on the distance d between the LED and the entrance surface. The illuminance uniformity increased with d but its increasing rate slowed down when d was beyond ~ 1.5 mm. When micro-patterns such as a lenticular lens array (LLA) or a serration pattern were formed on the entrance surface, the illuminance uniformity was improved substantially even for the case of very small d. At the same simulation condition, the lightguide with serration pattern showed a better uniformity than that with LLA pattern. Additional improvement could be achieved by changing the refractive index of the micro-patterns. These results suggest that using micro-patterns is a very effective way to reduce the bright spots due to their refracting function for the concentrated incident rays onto the LGP.

Development and Field Test of the NEXTSat-2 Synthetic Aperture Radar (SAR) Antenna Onboard Vehicle (차세대소형위성 2호 영상 레이다 안테나 개발 및 차량 탑재 시험)

  • Shin, Goo-Hwan;Lee, Jung-Su;Jang, Tae Seong;Kim, Dong-Guk;Jung, Young-Bae
    • Journal of Space Technology and Applications
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    • v.1 no.1
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    • pp.33-40
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    • 2021
  • Based on the requirements of a total weight of 42 kg or less, the NEXTSat-2 SAR (synthetic aperture radar) system was developed. As the NEXTSat-2 is a small-sized satellite, the SAR system was designed to account for about 40% of the dry mass of the payload relative to the total mass. Among the major components of the SAR system - which are an antenna, an RF transceiver, a baseband signal processor, and a power unit - a part with a particularly large dry mass is the antenna, the core of the SAR system. Whereas various selections are possible in consideration of gain and efficiency when designing the antenna, the micro-strip patch array antenna was adopted by reflecting the dry mass, power, and resolution required by the NEXTSat-2 project. In order to meet the mission requirement of the NEXTSat-2, the antenna was developed with a frequency of 9.65 GHz, a gain of 42.7 dBi, and a return loss of -15 dB. The performance of the antenna was verified by conducting a field test onboard the vehicle.

A CMOS 16:1 Binary-Tree Multiplexer applying Delay Compensation Techniques (딜레이 보상 기법을 적용한 바이너리-트리 구조의 CMOS 16:1 멀티플렉서)

  • Shon, Kwan-Su;Kim, Gil-Su;Kim, Kyu-Young;Kim, Soo-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.21-27
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    • 2008
  • This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.

Recent Progress in Micro In-Mold Process Technologies and Their Applications (마이크로 인몰드 공정기술 기반 전자소자 제조 및 응용)

  • Sung Hyun Kim;Young Woo Kwon;Suck Won Hong
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.2
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    • pp.1-12
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    • 2023
  • In the current era of the global mobile smart device revolution, electronic devices are required in all spaces that people interact with. The establishment of the internet of things (IoT) among smart devices has been recognized as a crucial objective to advance towards creating a comfortable and sustainable future society. In-mold electronic (IME) processes have gained significant industrial significance due to their ability to utilize conventional high-volume methods, which involve printing functional inks on 2D substrates, thermoforming them into 3D shapes, and injection-molded, manufacturing low-cost, lightweight, and functional components or devices. In this article, we provide an overview of IME and its latest advances in application. We review biomimetic nanomaterials for constructing self-supporting biosensor electronic materials on the body, energy storage devices, self-powered devices, and bio-monitoring technology from the perspective of in-mold electronic devices. We anticipate that IME device technology will play a critical role in establishing a human-machine interface (HMI) by converging with the rapidly growing flexible printed electronics technology, which is an integral component of the fourth industrial revolution.

Denoising of Infrared Images by an Adaptive Threshold Method in the Wavelet Transformed Domain (웨이브렛 변환 영역에서 적응문턱값을 이용한 적외선영상의 잡음제거)

  • Cho, Chang-Ho;Lee, Sang-Hyo;Lee, Jong-Yong;Cho, Do-Hyeon;Lee, Sang-Chuel
    • 전자공학회논문지 IE
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    • v.43 no.4
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    • pp.65-75
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    • 2006
  • This thesis deals with a wavelet-based method of denoising of infrared images contaminated with impulse noise and Gaussian noise, he method of thresholding the wavelet coefficients using derivatives and median absolute deviations of the wavelet coefficients of the detail subbands was proposed to effectively denoise infrared images with noises. Particularly, in order to eliminate the impulse noise the method of generating binary masks indicating locations of the impulse noise was selected. By this method, the threshold values dividing edges and noises were obtained more effectively proving the validity of the denoising method compared with the conventional wavelet shrinkage method.

Robust Skyline Extraction Algorithm For Mountainous Images (산악 영상에서의 지평선 검출 알고리즘)

  • Yang, Sung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.47 no.4
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    • pp.35-40
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    • 2010
  • Skyline extraction in mountainous images which has been used for navigation of vehicles or micro unmanned air vehicles is very hard to implement because of the complexity of skyline shapes, occlusions by environments, dfficulties to detect precise edges and noises in an image. In spite of these difficulties, skyline extraction is avery important theme that can be applied to the various fields of unmanned vehicles applications. In this paper, we developed a robust skyline extraction algorithm using two-scale canny edge images, topological information and location of the skyline in an image. Two-scale canny edge images are composed of High Scale Canny edge image that satisfies good localization criterion and Low Scale Canny edge image that satisfies good detection criterion. By applying each image to the proper steps of the algorithm, we could obtain good performance to extract skyline in images under complex environments. The performance of the proposed algorithm is proved by experimental results using various images and compared with an existing method.

Gravure Offset Printed on Fine Pattern by Developing Electrodes for the Ag Paste (Gravure Offset 인쇄에 의한 미세 전극용 Ag Paste 개발)

  • Lee, Sang-Yoon;Jang, Ah-Ram;Nam, Su-Yong
    • Journal of the Korean Graphic Arts Communication Society
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    • v.30 no.3
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    • pp.45-56
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    • 2012
  • Printing technology is accepted by appropriate technology that smart phones, tablet PC, display(LCD, OLED, etc.) precision recently in the electronics industry, the market grows, this process in the ongoing efforts to improve competitiveness through the development of innovative technologies. So printed electronics appeared by new concept. This technology development is applied on electronic components and circuits for the simplification of the production process and reduce processing costs. Low-temperature process making possible for widening, slimmer, lighter, and more flexible, plastic substrates, such as(flexible) easily by forming a thin film on a substrate has been studied. In the past, the formation of the electrode used a screen printing method. But the screen printing method is formation of fine patterns, high-speed printing, mass production is difficult. The roll-to-roll printing method as an alternative to screen printing to produce electronic devices by printing techniques that were used traditionally in the latest technology and processing techniques applied to precision control are very economical to implement fine-line printing equipment has been evaluated as. In order to function as electronic devices, especially the dozens of existing micro-level of non-dot print fine line printing is required, the line should not break at all, because according to the specifications required to fit the ink transfer conditions should be established. In this study of roll-to-roll printing conductive paste suitable for gravure offset printing by developing Ag paste for forming fine patterns to study the basic physical properties with the aim of this study were to.

Development of Microscale RF Chip Inductors for Wireless Communication Systems (무선통신시스템을 위한 극소형 RF 칩 인덕터의 개발)

  • 윤의중;김재욱;정영창;홍철호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.10
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    • pp.17-23
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    • 2003
  • In this study, microscale, high-performance, solenoid-type RF chip inductors were investigated. The size of the RF chip inductors fabricated in this work was 1.0${\times}$0.5${\times}$0.5㎣. The materials (96% Al2O3) and shape (I-type) of the core were determined by a Maxwell three-dimensional field simulator to maximize the performance of the inductors. The copper (Cu) wire with 40${\mu}{\textrm}{m}$ diameter was used as the coils. High frequency characteristics of the inductance (L), quality-factor (Q), and capacitance (C) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). The inductors developed have inductances of 11 to 39 nH and quality factors of 28 to 50 over the frequency ranges of 250MHz to 1 GHz, and show results comparable to those measured for the inductors prepared by CoilCraf $t^{Tm}$ that is one of the best chip inductor company in the world. The simulated data predicted the high-frequency data of the L, Q, and C of the inductors developed well.l.