• 전력전자학회논문지
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• 제22권4호
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• pp.297-304
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• 2017

The purpose of this paper is to analyze losses because of switching devices and the secondary side circuit diodes of 500 W full bridge dc-dc converter by applying gallium nitride (GaN) field-effect transistor (FET), which is one of the wide band gap devices. For the detailed device analysis, we translate the specific resistance relation caused by the GaN FET material property into algebraic expression, and investigate the influence of the GaN FET structure and characteristic on efficiency and system specifications. In addition, we mathematically compare the diode rectifier circuit loss, which is a full bridge dc-dc converter secondary side circuit, with the synchronous rectifier circuit loss using silicon metal-oxide semiconductor (Si MOSFET) or GaN FET, which produce the full bridge dc-dc converter analytical value validity to derive the final efficiency and loss. We also design the heat sink based on the mathematically derived loss value, and suggest the heat sink size by purpose and the heat divergence degree through simulation.

• 전력전자학회논문지
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• 제25권5호
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.18-19
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• 2017

This paper shows the design of the high voltage capacitor charger which using a modified series parallel resonant converter. The used silicon carbide Metal-Oxide Semiconductor Field Effect Transistor (SiC MOSFET) is proper for the few hundred kHz of high switching frequency to overcome the bulk resonant inductor and snubber capacitors. Furthermore, to increase the amount of the charging current, three phase delta transformer is used as well as the secondary sides are connected in parallel. In this paper, the design procedure of the high voltage capacitor charger is suggested and the output power is verified by the experimental results with the rated resistor load.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.145-146
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• 2002

Metal-Oxide-Semiconductor Field Effect Transistor(MOSFET)의 게이트 유전체로서 실리콘 산화막($SiO_2$)은 두께가 1.5nm 이하로 낮아질 경우 터널링 전류가 증가하여 누설 전류가 증가하게 된다. 이로 인해 사용 전력이 증가하게 되고, 소자의 성능을 떨어뜨리게 된다. 본 논문은 높은 유전상수와 넓은 에너지 밴드 갭을 갖는 $HfO_2$를 RF Magnetron Sputter를 이용하여 증착한 다음 RTA 열처리를 통하여 HfSixOy를 생성하여 전기적 특성을 측정하였다. 실험결과, 열처리 시간이 증가함에 따라 HfSixOy의 분포가 균일해지는 반면 두께가 얇아져서 누설 전류가 증가 하는 것으로 관찰되었다. $HfO_2$를 게이트 유전막으로 증착하였을 경우 $HfO_2/HfSixOy/Si$의 이중 박막 구조가 생겨 유전상수를 떨어뜨리는 반면, 실리콘 기판과 우수한 계면 특성을 갖는 HfSixOy만을 증착할 경우 양질의 단층 게이트 유전막으로 활용가능 할 것으로 사료된다.

• Journal of Power Electronics
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• 제17권6호
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• pp.1469-1479
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• 2017

Primary-side regulation (PSR) scheme is widely applied in low power applications, such as cell phone chargers, network adapters, and LED drivers. However, the efficiency and standby power requirements have been improved to a high standard due to the new trends of DOE (Department Of Energy) Level VI and COC (Code Of Conduct specifications) V5. The major drawbacks of PSR include poor regulation due to inaccurate feedback and difficulty in acquiring acceptable regulation. A novel adaptive blanking strategy for constant current and constant voltage regulation is proposed in this paper. An accurate model for the sample blanking time related to transformer leakage inductance and the metal-oxide-semiconductor field-effect transistor (MOSFET) parasitic capacitance is established. The proposed strategy can achieve accurate detection for ultra-low standby power. In addition, numerous control factors are analyzed in detail to eliminate the influence of leakage inductance on the loop stability. A dedicated controller integrated circuit (IC) with a power MOSFET is fabricated to verify the effectiveness of the proposed control strategy. Experimental results demonstrated that the prototype based on the proposed IC has excellent performance.

• Journal of Power Electronics
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• 제19권1호
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• pp.220-233
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• 2019

This work aims to study and analyze the various operating modes of universal power converter which is powered by solar and thermoelectric generators. The proposed converter is operated in a DC-DC (buck or boost mode) and DC-AC (single phase) inverter with high efficiency. DC power sources, such as solar photovoltaic (SPV) panels, thermoelectric generators (TEGs), and Li-ion battery, are selected as input to the proposed converter according to the nominal output voltage available/generated by these sources. The mode of selection and output power regulation are achieved via control of the metal-oxide semiconductor field-effect transistor (MOSFET) switches in the converter through the modified stepped perturb and observe (MSPO) algorithm. The MSPO duty cycle control algorithm effectively converts the unregulated DC power from the SPV/TEG into regulated DC for storing energy in a Li-ion battery or directly driving a DC load. In this work, the proposed power sources and converter are mathematically modelled using the Scilab-Xcos Simulink tool. The hardware prototype is designed for 200 W rating with a dsPIC30F4011 digital controller. The various output parameters, such as voltage ripple, current ripple, switching losses, and converter efficiency, are analyzed, and the proposed converter with a control circuit operates the converter closely at 97% efficiency.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.389-389
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• 2013

HfOx (Hafnium oxide)는 ~25의 고유전상수, 5.25 eV의 비교적 높은 Band-gap을 갖는 물질로 MOSFET (metal-oxide semiconductor field-effect-transistor) 구조의 Oxide 박막을 대체 가능한 물질로 연구가 지속되고 있다. 현재까지 진행된 대다수의 연구는 증착 조건에 따른 박막의 결정학적 및 전기적 특성에 대한 주제로 진행되었고 다양한 연구 결과가 보고된바 있다. 하지만 기존의 연구 기법은 박막의 nanomechanics 특성에 대한 연구가 부족하여 이를 보완하기 위한 연구가 절실하다. 따라서 본 연구에서는 HfOx 박막 내 포함된 산소가 고온 열처리 과정에서 빠져나감으로 인한 박막의 nanomechanics 특성을 확인하고자 하였다. 시료는 rf magnetron sputter를 이용하여Si (silicon) 기판위에 Hafnium target으로 산소유량(5, 10, 15 sccm)을 달리하여 증착하였고, 이후 furnace에서 $400^{\circ}C$에서 $1,000^{\circ}C$까지 질소분위기에서 20분간 열처리를 실시하였다. 실험결과 시료의 전기적 특성을 I-V 곡선을 측정하여 확인하였고, 증착 시 산소 유량이 5 sccm에서 15 sccm으로 증가함에 따라서 누설전류 특성은 급격히 향상되었고, 열처리 온도가 증가함에 따라 감소하는 특성을 나타내었다. 또한 시료의 nanomechanics 특성을 확인하기 위하여 nano-indenter를 이용하여 시료의 표면강도(surface hardness)와 탄성계수(elastic modulus)를 확인하였다. 측정결과 5 sccm 시료의 표면강도와 탄성계수는 상온에서 열처리 온도가 증가함에 따라 각각 7.75 GPa에서 9.19 GPa로, 그리고 133.83 GPa에서 126.64 GPa로 10, 15 sccm의 박막의 비하여 상대적으로 균일한 특성을 나타내었다. 이는 증착 시 박막 내 과포화된 산소가 열처리 과정에서 빠져나감으로 인한 것이며, 또한 과포화된 정도에 따라 더 적은 열처리 에너지에 의하여 박막을 빠져나감으로 인한 것으로 판단된다. 또한 열처리 과정에서 산소가 빠져나가는 상대적인 flux의 영향으로 인하여 박막의 mechanical한 균일도의 변화가 나타났다.

• 한국전기전자재료학회논문지
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• 제31권6호
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• pp.377-385
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• 2018

For the investigation of dopant profiles in implanted $Si_{1-x}Ge_x$, the implanted B and As profiles are measured using SIMS (secondary ion mass spectrometry). The fundamental ion-solid interactions of implantation in $Si_{1-x}Ge_x$ are discussed and explained using SRIM, UT-marlowe, and T-dyn programs. The annealed simulation profiles are also analyzed and compared with experimental data. In comparison with the SIMS data, the boron simulation results show 8% deviations of $R_p$ and 1.8% deviations of ${\Delta}R_p$ owing to relatively small lattice strain and relaxation on the sample surface. In comparison with the SIMS data, the simulation results show 4.7% deviations of $R_p$ and 8.1% deviations of ${\Delta}R_p$ in the arsenic implanted $Si_{0.2}Ge_{0.8}$ layer and 8.5% deviations of $R_p$ and 38% deviations of ${\Delta}R_p$ in the $Si_{0.5}Ge_{0.5}$ layer. An analytical method for obtaining the dopant profile is proposed and also compared with experimental and simulation data herein. For the high-speed CMOSFET (complementary metal oxide semiconductor field effect transistor) and HBT (heterojunction bipolar transistor), the study of dopant profiles in the $Si_{1-x}Ge_x$ layer becomes more important for accurate device scaling and fabrication technologies.

• 전기전자학회논문지
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• 제14권4호
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• pp.257-262
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• 2010

본 논문에서는 5.25 GHz에서 넓은 이득 제어범위를 갖는 저전력 가변 이득 프론트-엔드를 설계하였다. 넓은 이득 제어범위를 갖기 위해, 제안된 저잡음 증폭에서는 가변이득 증폭기의 소스에 p-타입 트랜지스터를 연결하였다. 이 방법을 통해 증폭기의 바이어스 전류와 소스 임피던스를 동시에 조절할 수 있었다. 따라서 제안된 저잡음 증폭기는 넓은 이득 제어범위를 갖는다. 믹서에서는 입력 트랜스컨덕턴스단으로 p-타입 트랜지스터를 사용한 폴디드 구조가 제안되었다. 이 구조에서 믹서는 작은 공급 전압에서 각 단에 필요한 만큼의 전류만 흘려주기 때문에 저전력에서도 작동을 할 수 있다. 제안된 프론트-엔드는 최대 33.2 dB의 이득과 17 dB의 넓은 이득 제어범위를 갖는다. 이 때, 잡음지수와 IIP3는 각각 4.8 dB, -8.5 dBm을 갖는다. 이러한 동작을 하는 동안, 제안된 회로는 최대 이득상태에서 7.1 mW, 최소 이득상태에서 2.6 mW의 적은 전력을 소비한다. 시뮬레이션 결과는 TSMC $0.18\;{\mu}m$ CMOS 공정에서 Cadence를 이용하여 얻어졌다.

• 센서학회지
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• 제20권3호
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• pp.156-161
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• 2011

We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.