• EDISON SW 활용 경진대회 논문집
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• 제4회(2015년)
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• pp.350-353
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• 2015

최근 에너지 효율과 소형화측면에서 한계를 보이는 Metal-Oxide-Semiconductor Field-Effect Transistor(MOSFET)을 대체할 수 있는 소자로 Tunneling FET(TFET)이 주목받고 있다. 본 논문에서는 탄소나노튜브(Carbon Nanotube, CNT) TFET을 시뮬레이션하여 전자회로의 기본 단위인 인버터(Inverter)를 설계한다. 설계한 인버터의 성능을 CNT-MOSFET 인버터와 비교하여 저전력 디지털 회로로써의 가능성을 확인한다.

• 한국전기전자재료학회논문지
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• 제28권4호
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• pp.222-228
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device, it is essential to increase its conductance. However, a trade-off relationship between the breakdown voltage and conductance of the device have been the critical difficulty to improve. In this paper, theoretical analysis of electrical benefits on single floating island power MOSFET is proposed. By the method, the optimization point has set defining the doping limit under single floating island structure. The numerical multiple 2.22 was obtained which indicates the doping limit of the original device, improving its ON state voltage drop by 45%.

• 한국전기전자재료학회논문지
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• 제28권4호
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• pp.218-221
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].

• 진공이야기
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• 제3권3호
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 추계학술대회
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• pp.115-117
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• 2022

피드백 전계 효과 트랜지스터(feedback field-effect transistor; FBFET)로 구성된 모놀리식 3차원 정적 랜덤 액세스 메모리(monolithic 3-dimensional static random access memory; M3D-SRAM)에 대해 TCAD(technology computer-aided design) 프로그램을 사용하여 전기적 특성을 조사하였다. FBFET로 구성된 M3D-SRAM(M3D-SRAM-FBFET)는 FDSOI(fully depleted silicon on insulator) 구조의 N형 FBFET와 N형 MOSFET(metal oxide semiconductor field effect transistor)로 이루어져 있으며 각각 하부와 상부에 위치한다. M3D-SRAM-FBFET의 메모리 동작 시, 공급 전압이 1.9 V에서 감소함에 따라 읽기 전류가 낮아졌으며, 공급 전압이 1.6 V 일 때 읽기 전류가 약 10배 감소하였다.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1497-1502
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• 2013

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.

• ETRI Journal
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• 제34권1호
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• pp.134-137
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• 2012

Power metal-oxide semiconductor field-effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double-diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. To overcome the tradeoff relationship, a super-junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on-state resistance of 1.2 $m{\Omega}-cm^2$ at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.

• ETRI Journal
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• 제27권4호
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• pp.449-452
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• 2005

The electrical characteristics of solid state devices such as the bipolar junction transistor (BJT), metal-oxide semiconductor field-effect transistor (MOSFET), and other active devices are altered by impinging photon radiation and temperature in the space environment. In this paper, the threshold voltage, the breakdown voltage, and the on-resistance for two kinds of MOSFETs (200 V and 100 V of $V_{DSS}$) are tested for ${\gamma}-irradiation$ and compared with the electrical specifications under the pre- and post-irradiation low dose rates of 4.97 and 9.55 rad/s as well as at a maximum total dose of 30 krad. In our experiment, the ${\gamma}-radiation$ facility using a low dose, available at Korea Atomic Energy Research Institute (KAERI), has been applied on two commercially available International Rectifier (IR) products, IRFP250 and IRF540.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.67-70
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• 2003

In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.