• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.61-61
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• 2000

Device의 고성능화를 위하여 소자의 고속화, 고집적화가 가속됨에 따라 SALICIDE Process가 더욱 절실하게 요구되고 있다. 이러한 SALICIDE Process의 재료로써는 metal/silicide 중에서 비저항이 가장 낮은 TiSi2(15-25$\mu$$\Omega$cm), CoSi2(17-25$\mu$$\Omega$cm)가 일반적으로 많이 연구되어 왔다. 그러나 Ti-silicide의 경우 Co-silicide는 배선 선폭의 감소에 따른 면저항 값의 변화가 작으며, 고온에서 안정하고, 도펀트 물질과 열역학적으로 안정하여 화합물을 형성하지 않는다는 장점이 있으마 Ti처럼 자연산화막을 제거할 수 없어 Si 기판위에 자연산화막이 존재시 균일한 실리사이드 박막을 형성할 수 없는 단점등을 가지고 있다. 본 연구에서는 Ti Capping layer 에 의한 균일한 Co-silicide의 형성을 일반적인 Si(100)기판과 SCl 방법에 의하여 chemical Oxide를 성장시킨 Si(100)기판의 경우에 대하여 연구하였다. 스퍼터링 방법에 의해 Co를 150 증착후 capping layer로써 TiN, Ti를 각각 100 씩 증착하였다. 열처리는 RTP를 이용하여 50$0^{\circ}C$~78$0^{\circ}C$까지 4$0^{\circ}C$ 구간으로 N2 분위기에서 30초 동안 열처리를 한후, selective metal strip XRD, TEM의 분석장비를 이용하여 관찰하였다. lst RTP후 selective metal strip 후 면저항의 측정과 XRD 분석결과 낮은 면저항을 갖는 CoSi2로의 상전이는 TiN capping과 Co 단일박막이 일반적인 Si(100)기판과 interfacial oxide가 존재하는 Si(100)기판위에서 Ti capping의 경우보다 낮은 온도에서 일어났다. 또한 CoSi에서 CoSi2으로 상전이는 일반적인 Si(100)기판위에서 보다 interfacial Oxide가 존재하는 Si(100)기판 위에 TiN capping과 Co 단일박막의 경우 열처리 후에도 Oxide가 존재하는 불균인한 CoSi2박막을 관찰하였으며, Ti capping의 경우 Oxise가 존재하지 않는 표면과 계면이 더 균일한 CoSi2 박막을 형성 할 수 있었다.

• Journal of Korea Foundry Society
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• v.17 no.1
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• pp.85-92
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• 1997

There has been a considerable interest to develop the silicide alloys as high temperature structural materials because of their excellent high temperature stability and strength, however, their lack of room temperature ductility and toughness was a main obstacle for the application. In order to improve ductility while maintaining good high temperature properties, possible refractory metal-silicide eutectic alloys composed of fine two phases were prepared by VAR(Vacuum Arc Remelting). Three silicide alloys, $Nb-Nb_3Si$, $Ti-Ti_5Si_3$, $V-V_3Si$, were selected as prospecting silicide eutectics and those high temperature characteristics were evaluated by high temperature compression test.

• Journal of the Semiconductor & Display Technology
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• v.7 no.2
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• pp.1-5
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• 2008

Silicide formation process and the formation sequence were investigated in this study. It was postulated that the formation of the second silicide phase involves glass formation between the first silicide phase and Si given that a thin metal film is deposited on a Si substrate. The concentration of glass was assumed to be located where the free energy of the liquid alloy with respect to the first nucleated compound and solid Si (${\Delta}$G') is most negative. It was also mentioned that the glass concentration is close to the composition of the second phase in order to achieve the maximum energy degradation. It was shown that the minimum ${\Delta}$G' concentration can be estimated by interpolating the portion of the liquidus where the liquid alloy is in equilibrium with the two solid constituents, namely the first compound phase and Si, thereby forming a hypothetical eutectic.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.64-67
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• 2000

Tungsten silicide(WSi$_2$) is proposed for the alternate gate electrode of ULSI MOS devices. Good structural property and low resistivity of WSi$_2$ deposited by a low pressure chemical vapor deposition(LPCVD) method directly on SiO$_2$ is obtained after annealing. Especially, WSi$_2$-SiO2 interface remains flat after annealing tungsten silicide at high temperature. Electrical characteristics of annealed WSi$_2$-SiO$_2$-Si(MOS) capacitors were improved in view of charge trapping.

• 전기의세계
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• v.35 no.10
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• pp.635-642
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• 1986

• 전기의세계
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• v.35 no.8
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• pp.483-492
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• 1986

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.122-126
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• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.

• Journal of the Korean Ceramic Society
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• v.38 no.10
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.3
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• pp.273-277
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• 2005

We prepared $0.25\~l.5um$ poly silicon gate array test group with $SiO_2$ spacers in order to employ NiCo composite salicide process from 15nm Ni/15nm Co/poly structure. We investigate the residual metal shape evolution by varying the rapid thermal silicide anneal temperature from $700^{\circ}C\;to\;1100^{\circ}C$. We observed the residual metals agglomerated into maze type and line type on $SiO_2$ field and silicide gate, respectively as temperature increased. We propose that lower silicide temperature would be favorable in newly proposed NiCo salicide in order to lessen the agglomeration causing the leakage and scum formation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.