• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.32-37
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• 2019

Titanium dioxide ($TiO_2$) is a promising dielectric material in the semiconductor industry for its high dielectric constant. However, for utilization on Si substrate, $TiO_2$ film meets with a difficulty due to the large leakage currents caused by its small conduction band energy offset from Si substrate. In this study, we propose an in-situ plasma oxidation process in plasma-enhanced atomic layer deposition (PE-ALD) system to form an oxide barrier layer which can reduce the leakage currents from Si substrate to $TiO_2$ film. $TiO_2$ film depositions were followed by the plasma oxidation process using tetrakis(dimethylamino)titanium (TDMAT) as a Ti precursor. In our result, $SiO_2$ layer was successfully introduced by the plasma oxidation process and was used as a barrier layer between the Si substrate and $TiO_2$ film. Metal-oxide-semiconductor ($TiN/TiO_2/P-type$ Si substrate) capacitor with plasma oxidation barrier layer showed improved C-V and I-V characteristics compared to that without the plasma oxidation barrier layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• Korean Journal of Materials Research
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• v.30 no.5
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• pp.239-245
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• 2020

Synthesizing one-dimensional nanostructures of oxide semiconductors is a promising approach to fabricate highefficiency photoelectrodes for hydrogen production from photoelectrochemical (PEC) water splitting. In this work, vertically aligned zinc oxide (ZnO) nanorod arrays are successfully synthesized on fluorine-doped-tin-oxide (FTO) coated glass substrate via seed-mediated hydrothermal synthesis method with the use of a ZnO nanoparticle seed layer, which is formed by thermally oxidizing a sputtered Zn metal thin film. The structural, optical and PEC properties of the ZnO nanorod arrays synthesized at varying levels of Zn sputtering power are examined to reveal that the optimum ZnO nanorod array can be obtained at a sputtering power of 20 W. The photocurrent density and the optimal photocurrent conversion efficiency obtained for the optimum ZnO nanorod array photoanode are 0.13 mA/㎠ and 0.49 %, respectively, at a potential of 0.85 V vs. RHE. These results provide a promising avenue to fabricating earth-abundant ZnO-based photoanodes for PEC water oxidation using facile hydrothermal synthesis.

• Journal of the Korean institute of surface engineering
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• v.54 no.5
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• pp.260-266
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• 2021

Synthesizing low-dimensional structures of oxide semiconductors is a promising approach to fabricate highly efficient gas sensors by means of possible enhancement in surface-to-volume ratios of their sensing materials. In this work, vertically aligned zinc oxide (ZnO) nanorods are successfully synthesized on a transparent glass substrate via seed-mediated hydrothermal synthesis method with the use of a ZnO nanoparticle seed layer, which is formed by thermally oxidizing a sputtered Zn metal film. Structural and optical characterization by x-ray diffraction (XRD), scanning electron microscopy (SEM), and Raman spectroscopy reveals the successful preparation of the ZnO nanorods array of the single hexagonal wurtzite crystalline phase. From gas sensing measurements for the nitrogen dioxide (NO₂) gas, the vertically aligned ZnO nanorod array is observed to have a highly responsive sensitivity to NO₂ gas at relatively low concentrations and operating temperatures, especially showing a high maximum sensitivity to NO₂ at 250 ℃ and a low NO₂ detection limit of 5 ppm in dry air. These results along with a facile fabrication process demonstrate that the ZnO nanorods synthesized on a transparent glass substrate are very promising for low-cost and high-performance NO₂ gas sensors.

• Journal of the Korean institute of surface engineering
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• v.56 no.4
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• pp.219-226
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• 2023

Utilizing low-dimensional structures of oxide semiconductors is a promising approach to fabricate relevant gas sensors by means of potential enhancement in surface-to-volume ratios of their sensing materials. In this work, vertically aligned cupric oxide (CuO) nanorods are successfully synthesized on a transparent glass substrate via seed-mediated hydrothermal synthesis method with the use of a CuO nanoparticle seed layer, which is formed by thermally oxidizing a sputtered Cu metal film. Structural and optical characterization by x-ray diffraction (XRD), scanning electron microscopy (SEM), and Raman spectroscopy reveals the successful preparation of the CuO nanorods array of the single monoclinic tenorite crystalline phase. From gas sensing measurements for the nitrogen monoxide (NO) gas, the vertically aligned CuO nanorod array is observed to have a highly responsive sensitivity to NO gas at relatively low concentrations and operating temperatures, especially showing a high maximum sensitivity to NO at 200 ℃ and a low NO detection limit of 2 ppm in dry air. These results along with a facile fabrication process demonstrate that the CuO nanorods synthesized on a transparent glass substrate are very promising for low-cost and high-performance NO gas sensors.

• Journal of the Korean Vacuum Society
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• v.2 no.2
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• pp.188-198
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• 1993

We have developed a technique for growing thin oxides (6~10 nm) by the Last step TCA method. N-channel metal-oxide-semiconductor (n-MOS) capacitor and n-channel metal-oxide-semiconductor field-effect transistor's (MOSFET's) having a gate oxide with chlorine incorporated $SiO_2/Si$ interface have been analyzed by electrical measurements and physical methods, such as secondary ion mass spectrometry (SIMS) and electron spectroscopy for chemical analysis (ESCA). The gate oxide grown with the Last strp TCA method has good characteristics as follows: the electron mobility of the MOSFET's with the Last step TCA method was increased by about 7% and the defect density at the $SiO_2/Si$ interface decreases slightly compared with that with No TCA method. In reliability estimation, the breakdown field was 18 MV/cm, 0.6 MV/cm higher than that of the gate oxide with No TCA method, and the lifetime estimated by TDDB measurement was longer than 20 years. The device lifetime estimated from hot-carrier reliability was proven to be enhanced. As the results, the gate oxide having a $SiO_2/Si$ interface incorporated with chlorine has good characteristics. Our new technique of Last step TCA method may be used to improve the endurance and retention of MOSFET's and to alleviate the degradation of thin oxides in short-channel MOS devices.

• 전자공학회논문지 IE
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• v.43 no.2
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• pp.7-10
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• 2006

A GaN-based metal-insulator-semiconductor (MIS) structure has been fabricated by using $BaTa_2O_6$ instead of conventional oxide as insulator gate. The leakage current o) films are in order of $10^{-12}-10^{-13}A/cm^2$ for GaN on $Al_2O_3$(0001) substrate and in order of $10^{-6}-10^{-7}A/cm^2$ for GaN on GaAs(001) substrate. The leakage current of thses films is governed by space-charge-limited current over 45 MV/cm in case of GaN on $Al_2O_3$(0001) substrate and by Poole-Frenkel emission in case of GaN on GaAs(001).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.178-178
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• 2010

With the scaling down of ULSI(Ultra Large Scale Integration) circuit of CMOS(Complementary Metal Oxide Semiconductor)based electronic devices, the electronic devices become more faster and smaller size that are promising field of semiconductor market. However, very narrow line width has some disadvantages. For example, because of narrow line width, deposition of conformal and thin barrier is difficult. Besides, proportion of barrier width is large, thus resistance is high. Conventional PVD(Physical Vapor Deposition) thin films are not able to gain a good quality and conformal layer. Hence, in order to get over these side effects, deposition of thin layer used of ALD(Atomic Layer Deposition) is important factor. Furthermore, it is essential that copper atomic diffusion into dielectric layer such as silicon oxide and hafnium oxide. If copper line is not surrounded by diffusion barrier, it cause the leakage current and devices degradation. There are some possible methods for improving the these secondary effects. In this study, TaNx, is used of Tertiarybutylimido tris (ethylamethlamino) tantalum (TBITEMAT), was deposited on the 24nm sized trench silicon oxide/silicon bi-layer substrate with good step coverage and high quality film using plasma enhanced atomic layer deposition (PEALD). And then copper was deposited on TaNx barrier using same deposition method. The thickness of TaNx was 4~5 nm. TaNx film was deposited the condition of under $300^{\circ}C$ and copper deposition temperature was under $120^{\circ}C$, and feeding time of TaNx and copper were 5 seconds and 5 seconds, relatively. Purge time of TaNx and copper films were 10 seconds and 6 seconds, relatively. XRD, TEM, AFM, I-V measurement(for testing leakage current and stability) were used to analyze this work. With this work, thin barrier layer(4~5nm) with deposited PEALD has good step coverage and good thermal stability. So the barrier properties of PEALD TaNx film are desirable for copper interconnection.