• Korean Journal of Materials Research
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• v.17 no.9
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• pp.453-457
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• 2007

Interest in use of ink-jet printing for pattern-on-demand fabrication of metal interconnects without complicated and wasteful etching process has been on rapid increase. However, ink-jet printing is a wet process and needs an additional thermal treatment such as an annealing process. Since a metal ink is a suspension containing metal nanoparticles and organic capping molecules to prevent aggregation of them, the microstructure of an ink-jet printed metal interconnect 'as dried' can be characterized as a stack of loosely packed nanoparticles. Therefore, during being treated thermally, an inkjet-printed interconnect is likely to evolve a characteristic microstructure, different from that of the conventionally vacuum-deposited metal films. Microstructure characteristics can significantly affect the corresponding electrical and mechanical properties. The characteristics of change in microstructure and electrical resistivity of inkjet-printed silver (Ag) films when annealed isothermally at a temperature between 170 and $240^{\circ}C$ were analyzed. The change in electrical resistivity was described using the first-order exponential decay kinetics. The corresponding activation energy of 0.44 eV was explained in terms of a thermally-activated mechanism, i.e., migration of point defects such as vacancy-oxygen pairs, rather than microstructure evolution such as grain growth or change in porosity.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.27-34
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• 2017

We investigated the feasibility of parylene F usage as an intermediate layer between a polydimethylsiloxane (PDMS) substrate and an Au thin-film interconnect as well as the swelling effect of PDMS substrate on the stretchable deformability of an Au thin film. The 150-nm-thick Au film, which was sputtered on a PDMS substrate without a parylene F layer, exhibited an initial resistance of $11.7{\Omega}$ and an overflow of its resistance at a tensile strain of 12.5%. On the other hand, the Au film, which was formed with a 150-nm-thick parylene F layer, revealed an much improved resistance characteristics: $1.21{\Omega}$ as its initial resistance and $246{\Omega}$ at its 30% elongation state. With swelling of PDMS substrate, the resistance of an Au film substantially decreased to $14.4{\Omega}$ at 30% tensile strain.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.16-25
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• 2002

This paper presents a methodology and application for extracting parasitic inductances in a multi-level interconnect semiconductor structure by a numerical technique. In order to calculate the parasitic inductances, the distrubution of electric potential and current density in the metal lines are calculated by finite element method (FEM). Thereafter, the magneto-static energy caused by the current density in metal lines was calculated. The result of simulation is compared with the result of Grover equation about analytic simple structures, and 4 bit ROM array with a dimension of $13{\times}10.25{\times}8.25{\mu}m^3$ was simulated to extract the parasitic inductnaces. In this calculation, 6,358 nodes with 31,941 tetrahedra were used in ULTRA 10 workstation. The total CPU time for the simulation was about 150 seconds, while the memory size of 20 MB was required.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.18-21
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• 2002

As the mask design rules get smaller, the probability of the process failure becomes higher due to the narrow overlay margin between the contact and metal interconnect layers. To obtain the minimum process margin, a tabbing and cutting method is applied with the rule based optical proximity correction to the metal layer, so that the protection to bridge problems caused by the insufficient space margin between the metal layers can be accomplished. The side-lobe phenomenon from the attenuated phase shift mask with the tight design nile is analyzed through the aerial image simulation for test patterns with variation of the process parameters such as numerical aperture, transmission rate, and partial coherence. The corrected patterns are finally generated by the rules extracted from the side-lobe simulation.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.209-212
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• 2002

As the mask design rules get smaller, the probability of the process failure becomes higher doc to the narrow overlay margin between the contact and metal interconnect layers. To obtain the minimum process margin, a tabbing and cutting method Is applied with the rule based optical\ulcorner proximity correction to the metal layer, so that the protection to bridge problems caused by the insufficient space margin between the metal layers can be accomplished. The side-lobe phenomenon from the attenuated phase shift mask with the tight design rule is analyzed through the aerial image simulation for test patterns with variation of the process parameters such as numerical aperture, transmission rate, and partial coherence. The corrected patterns are finally generated by the rules extracted from the side-lobe simulation.

• ETRI Journal
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• v.44 no.1
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• pp.147-154
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• 2022

We demonstrate a new double-layer structure for stretchable interconnects, where the top surface of a serpentine polyimide support is coated with a thin eutectic gallium-indium liquid metal layer. Because the liquid metal layer is constantly fixed on the solid serpentine body in this liquid-on-solid structure, the overall stretching is accomplished by widening the solid frame itself, with little variation in the total length and cross-sectional area of the current path. Therefore, we can achieve both invariant resistance and infinite fatigue life by combining the stretchable configuration of the underlying body with the freely deformable nature of the top liquid conductor. Further, we fabricated various types of double-layer interconnects as narrow as 10 ㎛ using the roll-painting and lift-off patterning technique based on conventional photolithography and quantitatively validated their beneficial properties. The new interconnecting structure is expected to be widely used in applications requiring high-performance and high-density stretchable circuits owing to its superior reliability and capability to be monolithically integrated with thin-film devices.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.19-26
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• 2017

Stretchable deformation-resistance characteristics of Au, Pt, and Cu films were measured for the stretchable packaging structure where a parylene F was used as an intermediate layer between a PDMS substrate and a metal thin film. The 150 nm-thick Au and Pt films, sputtered on the parylene F-coated PDMS substrate, exhibited the initial resistances of $1.56{\Omega}$ and $5.53{\Omega}$, respectively. The resistance increase ratios at 30% tensile strain were measured as 7 and 18 for Au film and Pt film, respectively. The 150 nm-thick Cu film, sputtered on the parylene F-coated PDMS substrate, exhibited a very poor stretchability compared to Au and Pt films. Its resistance was initially $18.71{\Omega}$, rapidly increased with applying tensile deformation, and finally became open at 5% tensile strain.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.57-57
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• 2009

반도체 device가 고집적화 및 다층화 되어짐에 따라 현재 사용되고 있는 구리 interconnect의 확산방지막인 Ta/TaN은 많은 문제가 발생하고 있다. 고집적화 된 반도체 소자에 적용시키기에는 Ta/TaN 확산 방지막의 고유 저항값이 매우 크고, 구리의 증착에 필요한 seed layer의 크기도 문제화 된다고 보고되어지고 있다. 이러한 이유로 인해 점차 고집적화 되어지는 반도체 기술에 맞추어 새로운 확산 방지막에 대한 연구가 현재 활발히 이루어지고 있다. 이에 새로운 확산 방지막으로써 대두되고 연구되고 있는 재료가 Ruthenium (Ru)이다. Ru은 공기 중에서 매우 안정하고 고유저항 값 또한 $13\;{\mu}{\Omega}\;cm$의 Ta에 비해 $7.1\;{\mu}{\Omega}\;cm$의 매우 작은 고유저항 특성을 가지고 있다. 또한, Ru은 구리와의 우수한 접착성으로 인해 구리의 interconnect의 형성에 있어 seed layer가 필요하지 않을 뿐만 아니라 높은 annealing 온도에서도 무시할 만큼 작은 solid solubility를 가지며 구리와의 계면에서 새로운 화합물을 형성하지 않으며 annealing시 구리의 delamination을 유발시키지도 않는다. 이에 따라, 평탄화와 소자 분리를 위하여 chemical mechanical planarization (CMP) 공정이 필요하게 되었다. 하지만, Ru의 noble한 성질과 Ru 확산방지막 CMP공정 시 노출되는 다른 이종 물질 사이의 최적화 된 selectivity를 구현하는데 많은 어려움이 있다. 이로인해 Ru 확산 방지막을 위한 CMP slurry에 대한 연구는 아직 미흡한 수준이다. 본 연구에서는 Ru이 확산방지막으로 사용되었을 때 이를 위한 CMP slurry에 대한 평가와 연구가 이루어졌다. Slurry 조성과 농도 및 pH에 따른 전기 화학적 분석을 통하여 slurry 내에서 각각의 막질들이 어떠한 상태로 존재하는지 분석해 보았다. 또한, Ru을 비롯한 이종막질들의 etch rate, removal rate와 selectivity에 대한 연구가 진행되었다. 최종적으로 Ru 확산방지막 CMP를 위한 최적화된 slurry를 제안하였다.

• Journal of the Korean institute of surface engineering
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• v.57 no.3
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• pp.125-139
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• 2024

As the limits of semiconductor integration are approached, the challenges in semiconductor processes have intensified. And, for the production of semiconductors with dimensions under a few nanometers and to resolve the issues related to nanoscale device fabrication, research on atomic layer etching (ALE) technology has been conducted. The investigation related to ALE encompasses not only silicon and dielectric materials but also metallic materials. Particularly, there is an increasing need for ALE in next-generation metal materials that could replace copper in interconnect materials. This brief review will summarize the concept and methods of ALE and describe recent studies on potential next-generation metal replacements for copper, along with their ALE processes.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.27-33
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• 2005

The effect of microstructure on alternating current-induced damage in 200 and 300 nm thick polycrystalline sputtered Cu lines on Si substrates has been investigated. Alternating currents were used to generate temperature cycles (with ranges from 100 to $300^{\circ}C$) and thermal strains (with ranges from 0.14 to $0.42\%$) in the Cu lines at a frequency of 10 kHz. Fatigue loading caused the development of severe surface roughness that was localized within individual grains which depends severely on grain orientations.