• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.163-166
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• 2002

We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm， so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.832-835
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• 2001

We report the structural and electrical properties of hafnium oxide (HfO$_2$) films with tungsten silicide (WSi$_2$) metal gate. In this study, HfO$_2$thin films were fabricated by oxidation of sputtered Hf metal films on Si, and WSi$_2$was deposited directly on HfO$_2$by LPCVD. The hysteresis windows in C-V curves of the WSi$_2$HfO$_2$/Si MOS capacitors were negligible (<20 mV), and had no dependence on frequency from 10 kHz to 1 MHz and bias ramp rate from 10 mV to 1 V. In addition, leakage current was very low in the range of 10$^{-9}$ ~10$^{-10}$ A to ~ 1 V, which was due to the formation of interfacial hafnium silicate layer between HfO$_2$and Si. After PMA (post metallization annealing) of the WSi$_2$/HfO$_2$/Si MOS capacitors at 500 $^{\circ}C$ EOT (equivalent oxide thickness) was reduced from 26 to 22 $\AA$ and the leakage current was reduced by approximately one order as compared to that measured before annealing. These results indicate that the effect of fluorine diffusion is negligible and annealing minimizes the etching damage.

• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1619-1626
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• 2017

Electronic components that are used in high-level radiation environment require a semiconductor device having a radiation-hardened characteristic. In this paper, we proposed a radiation-hardened I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistors) using a layout modification technique only. The proposed I-gate n-MOSFET structure is modified as an I-shaped gate poly in order to mitigate a radiation-induced leakage current in the standard n-MOSFET structure. For verification of its radiation-hardened characteristic, the M&S (Modeling and Simulation) of the 3D (3-Dimension) structure is performed by TCAD (Technology Computer Aided Design) tool. In addition, we carried out an evaluation test using a $Co^{60}$ gamma-ray source of 10kGy(Si)/h. As a result, we have confirmed the radiation-hardened level up to a total ionizing dose of 20kGy(Si).

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.25-29
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• 2008

Reliability and performance in metal gate/high-k device with multiple gate dielectrics were investigated. MOSFETs with a thin $HfSiO_x$ layer on a thermal Si02 dielectric as gate dielectrics exhibit excellent mobility and low interface trap density. However, the distribution of threshold voltages of $HfSiO_x/SiO_2$ stack devices were wider than those of $SiO_2$ and $HfSiO_x$ single layer devices due to the penetration of Hf and/or intermixing of $HfSiO_x$ with underlying $SiO_2$. The results of TZDB and SILC characteristics suggested that a certain portion of $HfSiO_x$ layer reacted with the underlying thick $SiO_2$ layer, which in turn affected the reliability characteristics.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• ETRI Journal
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• v.32 no.4
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• pp.530-539
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• 2010

As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, quantum mechanical effects are expected to become more and more important. Accurate quantum transport simulators are required to explore the essential device physics as a design aid. However, because of the complexity of the analysis, it has been necessary to simulate the quantum mechanical model with high speed and accuracy. In this paper, the modeling of double gate MOSFET based on an adaptive neuro-fuzzy inference system (ANFIS) is presented. The ANFIS model reduces the computational time while keeping the accuracy of physics-based models, like non-equilibrium Green's function formalism. Finally, we import the ANFIS model into the circuit simulator software as a subcircuit. The results show that the compact model based on ANFIS is an efficient tool for the simulation of nanoscale circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.43-50
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• 2007

In a high-speed flash style or a pipelining style analog-to-digital converter (A/D converter), the DC reference fluctuation caused by external noises becomes serious, as the sampling frequency is increased. To reduce the fluctuations in conventional A/D converters, capacitors have been simply used, but the layout area was large. Instead of capacitors, a low-noise and small-size DC reference circuit based on transmission gate (TG) is proposed in this paper. In order to verify the proposed technique, we designed and manufactured a 6-bit 2GSPS CMOS A/D converter. The A/D converter is designed with a 0.18um 1-poly 6-metal n-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies the chip area of 977um by 1040um. The measured result shows that SNDR is 36.25 dB and INL/DNL is within 0.5LSB, even though the DC reference fluctuation is serious.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.359-359
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• 2010

IGBT(Insulated Gate Bipolar Transistor) 란 MOS(Metal Oxide Silicon) 와 Bipolar 기술의 결정체로 낮은 순방향 손실(Low Saturation)과 빠른 Speed를 특징으로 기존의 Thyristor, BJT, MOSFET 등으로 실현 불가능한 분양의 응용처를 대상으로 적용이 확대 되고 있고, 300V 이상의 High Power Application 영역에서 널리 사용되고 있는 고효율, 고속의 전력 시스템에 있어서 필수적으로 이용되는 Power Device이다. IGBT는 출력 특성 면에서 Bipolar Transistor 이상의 전류 능력을 가지고 있고 입력 특성 면에서 MOSFET과 같이 Gate 구동 특성을 갖기 때문에 High Switching, High Power에 적용이 가능한 소자이다. 반면에, Conventional IGBT는 MOSFET과 달리 IGBT 내부에 Anti-Parallel Diode가 없기 때문에 Inductive Load Application 적용시에는 별도의 Free Wheeling Diode가 필요하다. 그래서, 본 논문에서 별도의 Anti-Parallel Diode의 추가 없이도 Inductive Load Application에 적용 가능한 RC IGBT를 적용하여 600V/15A급 Three Phase Inverter Module을 제안 하고자 한다.